Subzero: Clean up some uses of *_cast<>.

src/IceTargetLoweringX86BaseImpl.h

 //===- subzero/src/IceTargetLoweringX86BaseImpl.h - x86 lowering -*- C++ -*-==//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 2210 matching lines @@
     _div(T, Src1, T_edx);
     _mov(Dest, T);
   } break;
   case InstArithmetic::Sdiv:
     // TODO(stichnot): Enable this after doing better performance and cross
     // testing.
     if (false && Ctx->getFlags().getOptLevel() >= Opt_1) {
       // Optimize division by constant power of 2, but not for Om1 or O0, just
       // to keep things simple there.
       if (auto *C = llvm::dyn_cast<ConstantInteger32>(Src1)) {
-        int32_t Divisor = C->getValue();
-        uint32_t UDivisor = static_cast<uint32_t>(Divisor);
+        const int32_t Divisor = C->getValue();
+        const uint32_t UDivisor = Divisor;
         if (Divisor > 0 && llvm::isPowerOf2_32(UDivisor)) {
           uint32_t LogDiv = llvm::Log2_32(UDivisor);
           // LLVM does the following for dest=src/(1<<log):
           //   t=src
           //   sar t,typewidth-1 // -1 if src is negative, 0 if not
           //   shr t,typewidth-log
           //   add t,src
           //   sar t,log
           //   dest=t
           uint32_t TypeWidth = Traits::X86_CHAR_BIT * typeWidthInBytes(Ty);
@@ skipping 68 matching lines @@
     _div(T_edx, Src1, T);
     _mov(Dest, T_edx);
   } break;
   case InstArithmetic::Srem: {
     // TODO(stichnot): Enable this after doing better performance and cross
     // testing.
     if (false && Ctx->getFlags().getOptLevel() >= Opt_1) {
       // Optimize mod by constant power of 2, but not for Om1 or O0, just to
       // keep things simple there.
       if (auto *C = llvm::dyn_cast<ConstantInteger32>(Src1)) {
-        int32_t Divisor = C->getValue();
-        uint32_t UDivisor = static_cast<uint32_t>(Divisor);
+        const int32_t Divisor = C->getValue();
+        const uint32_t UDivisor = Divisor;
         if (Divisor > 0 && llvm::isPowerOf2_32(UDivisor)) {
           uint32_t LogDiv = llvm::Log2_32(UDivisor);
           // LLVM does the following for dest=src%(1<<log):
           //   t=src
           //   sar t,typewidth-1 // -1 if src is negative, 0 if not
           //   shr t,typewidth-log
           //   add t,src
           //   and t, -(1<<log)
           //   sub t,src
           //   neg t
@@ skipping 94 matching lines @@
   Operand *Cond = Br->getCondition();
 
   // Handle folding opportunities.
   if (const Inst *Producer = FoldingInfo.getProducerFor(Cond)) {
     assert(Producer->isDeleted());
     switch (BoolFolding<Traits>::getProducerKind(Producer)) {
     default:
       break;
     case BoolFolding<Traits>::PK_Icmp32:
     case BoolFolding<Traits>::PK_Icmp64: {
-      lowerIcmpAndConsumer(llvm::dyn_cast<InstIcmp>(Producer), Br);
+      lowerIcmpAndConsumer(llvm::cast<InstIcmp>(Producer), Br);
       return;
     }
     case BoolFolding<Traits>::PK_Fcmp: {
-      lowerFcmpAndConsumer(llvm::dyn_cast<InstFcmp>(Producer), Br);
+      lowerFcmpAndConsumer(llvm::cast<InstFcmp>(Producer), Br);
       return;
     }
     case BoolFolding<Traits>::PK_Arith: {
-      lowerArithAndConsumer(llvm::dyn_cast<InstArithmetic>(Producer), Br);
+      lowerArithAndConsumer(llvm::cast<InstArithmetic>(Producer), Br);
       return;
     }
     }
   }
   Operand *Src0 = legalize(Cond, Legal_Reg | Legal_Mem);
   Constant *Zero = Ctx->getConstantZero(IceType_i32);
   _cmp(Src0, Zero);
   _br(Traits::Cond::Br_ne, Br->getTargetTrue(), Br->getTargetFalse());
 }
 
@@ skipping 634 matching lines @@
     }
     break;
   }
   }
 }
 
 template <typename TraitsType>
 void TargetX86Base<TraitsType>::lowerExtractElement(
     const InstExtractElement *Instr) {
   Operand *SourceVectNotLegalized = Instr->getSrc(0);
-  ConstantInteger32 *ElementIndex =
-      llvm::dyn_cast<ConstantInteger32>(Instr->getSrc(1));
+  auto *ElementIndex = llvm::dyn_cast<ConstantInteger32>(Instr->getSrc(1));
   // Only constant indices are allowed in PNaCl IR.
   assert(ElementIndex);
 
   unsigned Index = ElementIndex->getValue();
   Type Ty = SourceVectNotLegalized->getType();
   Type ElementTy = typeElementType(Ty);
   Type InVectorElementTy = Traits::getInVectorElementType(Ty);
 
   // TODO(wala): Determine the best lowering sequences for each type.
   bool CanUsePextr = Ty == IceType_v8i16 || Ty == IceType_v8i1 ||
@@ skipping 99 matching lines @@
   //   j<C1> label        /* only if C1 != Br_None */
   //   j<C2> label        /* only if C2 != Br_None */
   //   FakeUse(a)         /* only if C1 != Br_None */
   //   mov a, !<default>  /* only if C1 != Br_None */
   //   label:             /* only if C1 != Br_None */
   //
   // setcc lowering when C1 != Br_None && C2 == Br_None:
   //   ucomiss b, c       /* but swap b,c order if SwapOperands==true */
   //   setcc a, C1
   InstFcmp::FCond Condition = Fcmp->getCondition();
-  size_t Index = static_cast<size_t>(Condition);
-  assert(Index < Traits::TableFcmpSize);
-  if (Traits::TableFcmp[Index].SwapScalarOperands)
+  assert(Condition < Traits::TableFcmpSize);
+  if (Traits::TableFcmp[Condition].SwapScalarOperands)
     std::swap(Src0, Src1);
-  bool HasC1 = (Traits::TableFcmp[Index].C1 != Traits::Cond::Br_None);
-  bool HasC2 = (Traits::TableFcmp[Index].C2 != Traits::Cond::Br_None);
+  const bool HasC1 = (Traits::TableFcmp[Condition].C1 != Traits::Cond::Br_None);
+  const bool HasC2 = (Traits::TableFcmp[Condition].C2 != Traits::Cond::Br_None);
   if (HasC1) {
     Src0 = legalize(Src0);
     Operand *Src1RM = legalize(Src1, Legal_Reg | Legal_Mem);
     Variable *T = nullptr;
     _mov(T, Src0);
     _ucomiss(T, Src1RM);
     if (!HasC2) {
-      assert(Traits::TableFcmp[Index].Default);
-      setccOrConsumer(Traits::TableFcmp[Index].C1, Dest, Consumer);
+      assert(Traits::TableFcmp[Condition].Default);
+      setccOrConsumer(Traits::TableFcmp[Condition].C1, Dest, Consumer);
       return;
     }
   }
-  int32_t IntDefault = Traits::TableFcmp[Index].Default;
+  int32_t IntDefault = Traits::TableFcmp[Condition].Default;
   if (Consumer == nullptr) {
     Constant *Default = Ctx->getConstantInt(Dest->getType(), IntDefault);
     _mov(Dest, Default);
     if (HasC1) {
       InstX86Label *Label = InstX86Label::create(Func, this);
-      _br(Traits::TableFcmp[Index].C1, Label);
+      _br(Traits::TableFcmp[Condition].C1, Label);
       if (HasC2) {
-        _br(Traits::TableFcmp[Index].C2, Label);
+        _br(Traits::TableFcmp[Condition].C2, Label);
       }
       Constant *NonDefault = Ctx->getConstantInt(Dest->getType(), !IntDefault);
       _redefined(_mov(Dest, NonDefault));
       Context.insert(Label);
     }
     return;
   }
   if (const auto *Br = llvm::dyn_cast<InstBr>(Consumer)) {
     CfgNode *TrueSucc = Br->getTargetTrue();
     CfgNode *FalseSucc = Br->getTargetFalse();
     if (IntDefault != 0)
       std::swap(TrueSucc, FalseSucc);
     if (HasC1) {
-      _br(Traits::TableFcmp[Index].C1, FalseSucc);
+      _br(Traits::TableFcmp[Condition].C1, FalseSucc);
       if (HasC2) {
-        _br(Traits::TableFcmp[Index].C2, FalseSucc);
+        _br(Traits::TableFcmp[Condition].C2, FalseSucc);
       }
       _br(TrueSucc);
       return;
     }
     _br(FalseSucc);
     return;
   }
   if (auto *Select = llvm::dyn_cast<InstSelect>(Consumer)) {
     Operand *SrcT = Select->getTrueOperand();
     Operand *SrcF = Select->getFalseOperand();
     Variable *SelectDest = Select->getDest();
     if (IntDefault != 0)
       std::swap(SrcT, SrcF);
     lowerMove(SelectDest, SrcF, false);
     if (HasC1) {
       InstX86Label *Label = InstX86Label::create(Func, this);
-      _br(Traits::TableFcmp[Index].C1, Label);
+      _br(Traits::TableFcmp[Condition].C1, Label);
       if (HasC2) {
-        _br(Traits::TableFcmp[Index].C2, Label);
+        _br(Traits::TableFcmp[Condition].C2, Label);
       }
       static constexpr bool IsRedefinition = true;
       lowerMove(SelectDest, SrcT, IsRedefinition);
       Context.insert(Label);
     }
     return;
   }
   llvm::report_fatal_error("Unexpected consumer type");
 }
 
 template <typename TraitsType>
 void TargetX86Base<TraitsType>::lowerFcmpVector(const InstFcmp *Fcmp) {
   Operand *Src0 = Fcmp->getSrc(0);
   Operand *Src1 = Fcmp->getSrc(1);
   Variable *Dest = Fcmp->getDest();
 
   if (!isVectorType(Dest->getType()))
     llvm::report_fatal_error("Expected vector compare");
 
   InstFcmp::FCond Condition = Fcmp->getCondition();
-  size_t Index = static_cast<size_t>(Condition);
-  assert(Index < Traits::TableFcmpSize);
+  assert(Condition < Traits::TableFcmpSize);
 
-  if (Traits::TableFcmp[Index].SwapVectorOperands)
+  if (Traits::TableFcmp[Condition].SwapVectorOperands)
     std::swap(Src0, Src1);
 
   Variable *T = nullptr;
 
   if (Condition == InstFcmp::True) {
     // makeVectorOfOnes() requires an integer vector type.
     T = makeVectorOfMinusOnes(IceType_v4i32);
   } else if (Condition == InstFcmp::False) {
     T = makeVectorOfZeros(Dest->getType());
   } else {
     Operand *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
     Operand *Src1RM = legalize(Src1, Legal_Reg | Legal_Mem);
     if (llvm::isa<X86OperandMem>(Src1RM))
       Src1RM = legalizeToReg(Src1RM);
 
     switch (Condition) {
     default: {
-      CmppsCond Predicate = Traits::TableFcmp[Index].Predicate;
+      const CmppsCond Predicate = Traits::TableFcmp[Condition].Predicate;
       assert(Predicate != Traits::Cond::Cmpps_Invalid);
       T = makeReg(Src0RM->getType());
       _movp(T, Src0RM);
       _cmpps(T, Src1RM, Predicate);
     } break;
     case InstFcmp::One: {
       // Check both unequal and ordered.
       T = makeReg(Src0RM->getType());
       Variable *T2 = makeReg(Src0RM->getType());
       _movp(T, Src0RM);
@@ skipping 181 matching lines @@
 template <typename TraitsType>
 template <typename T>
 typename std::enable_if<!T::Is64Bit, void>::type
 TargetX86Base<TraitsType>::lowerIcmp64(const InstIcmp *Icmp,
                                        const Inst *Consumer) {
   // a=icmp cond, b, c ==> cmp b,c; a=1; br cond,L1; FakeUse(a); a=0; L1:
   Operand *Src0 = legalize(Icmp->getSrc(0));
   Operand *Src1 = legalize(Icmp->getSrc(1));
   Variable *Dest = Icmp->getDest();
   InstIcmp::ICond Condition = Icmp->getCondition();
-  size_t Index = static_cast<size_t>(Condition);
-  assert(Index < Traits::TableIcmp64Size);
+  assert(Condition < Traits::TableIcmp64Size);
   Operand *Src0LoRM = nullptr;
   Operand *Src0HiRM = nullptr;
   // Legalize the portions of Src0 that are going to be needed.
   if (isZero(Src1)) {
     switch (Condition) {
     default:
       llvm_unreachable("unexpected condition");
       break;
     // These two are not optimized, so we fall through to the general case,
     // which needs the upper and lower halves legalized.
@@ skipping 71 matching lines @@
   // Handle general compares.
   Operand *Src1LoRI = legalize(loOperand(Src1), Legal_Reg | Legal_Imm);
   Operand *Src1HiRI = legalize(hiOperand(Src1), Legal_Reg | Legal_Imm);
   if (Consumer == nullptr) {
     Constant *Zero = Ctx->getConstantInt(Dest->getType(), 0);
     Constant *One = Ctx->getConstantInt(Dest->getType(), 1);
     InstX86Label *LabelFalse = InstX86Label::create(Func, this);
     InstX86Label *LabelTrue = InstX86Label::create(Func, this);
     _mov(Dest, One);
     _cmp(Src0HiRM, Src1HiRI);
-    if (Traits::TableIcmp64[Index].C1 != Traits::Cond::Br_None)
-      _br(Traits::TableIcmp64[Index].C1, LabelTrue);
-    if (Traits::TableIcmp64[Index].C2 != Traits::Cond::Br_None)
-      _br(Traits::TableIcmp64[Index].C2, LabelFalse);
+    if (Traits::TableIcmp64[Condition].C1 != Traits::Cond::Br_None)
+      _br(Traits::TableIcmp64[Condition].C1, LabelTrue);
+    if (Traits::TableIcmp64[Condition].C2 != Traits::Cond::Br_None)
+      _br(Traits::TableIcmp64[Condition].C2, LabelFalse);
     _cmp(Src0LoRM, Src1LoRI);
-    _br(Traits::TableIcmp64[Index].C3, LabelTrue);
+    _br(Traits::TableIcmp64[Condition].C3, LabelTrue);
     Context.insert(LabelFalse);
     _redefined(_mov(Dest, Zero));
     Context.insert(LabelTrue);
     return;
   }
   if (const auto *Br = llvm::dyn_cast<InstBr>(Consumer)) {
     _cmp(Src0HiRM, Src1HiRI);
-    if (Traits::TableIcmp64[Index].C1 != Traits::Cond::Br_None)
-      _br(Traits::TableIcmp64[Index].C1, Br->getTargetTrue());
-    if (Traits::TableIcmp64[Index].C2 != Traits::Cond::Br_None)
-      _br(Traits::TableIcmp64[Index].C2, Br->getTargetFalse());
+    if (Traits::TableIcmp64[Condition].C1 != Traits::Cond::Br_None)
+      _br(Traits::TableIcmp64[Condition].C1, Br->getTargetTrue());
+    if (Traits::TableIcmp64[Condition].C2 != Traits::Cond::Br_None)
+      _br(Traits::TableIcmp64[Condition].C2, Br->getTargetFalse());
     _cmp(Src0LoRM, Src1LoRI);
-    _br(Traits::TableIcmp64[Index].C3, Br->getTargetTrue(),
+    _br(Traits::TableIcmp64[Condition].C3, Br->getTargetTrue(),
         Br->getTargetFalse());
     return;
   }
   if (auto *Select = llvm::dyn_cast<InstSelect>(Consumer)) {
     Operand *SrcT = Select->getTrueOperand();
     Operand *SrcF = Select->getFalseOperand();
     Variable *SelectDest = Select->getDest();
     InstX86Label *LabelFalse = InstX86Label::create(Func, this);
     InstX86Label *LabelTrue = InstX86Label::create(Func, this);
     lowerMove(SelectDest, SrcT, false);
     _cmp(Src0HiRM, Src1HiRI);
-    if (Traits::TableIcmp64[Index].C1 != Traits::Cond::Br_None)
-      _br(Traits::TableIcmp64[Index].C1, LabelTrue);
-    if (Traits::TableIcmp64[Index].C2 != Traits::Cond::Br_None)
-      _br(Traits::TableIcmp64[Index].C2, LabelFalse);
+    if (Traits::TableIcmp64[Condition].C1 != Traits::Cond::Br_None)
+      _br(Traits::TableIcmp64[Condition].C1, LabelTrue);
+    if (Traits::TableIcmp64[Condition].C2 != Traits::Cond::Br_None)
+      _br(Traits::TableIcmp64[Condition].C2, LabelFalse);
     _cmp(Src0LoRM, Src1LoRI);
-    _br(Traits::TableIcmp64[Index].C3, LabelTrue);
+    _br(Traits::TableIcmp64[Condition].C3, LabelTrue);
     Context.insert(LabelFalse);
     static constexpr bool IsRedefinition = true;
     lowerMove(SelectDest, SrcF, IsRedefinition);
     Context.insert(LabelTrue);
     return;
   }
   llvm::report_fatal_error("Unexpected consumer type");
 }
 
 template <typename TraitsType>
@@ skipping 85 matching lines @@
     return;
   }
   llvm::report_fatal_error("Unexpected consumer type");
 }
 
 template <typename TraitsType>
 void TargetX86Base<TraitsType>::lowerInsertElement(
     const InstInsertElement *Instr) {
   Operand *SourceVectNotLegalized = Instr->getSrc(0);
   Operand *ElementToInsertNotLegalized = Instr->getSrc(1);
-  ConstantInteger32 *ElementIndex =
-      llvm::dyn_cast<ConstantInteger32>(Instr->getSrc(2));
+  auto *ElementIndex = llvm::dyn_cast<ConstantInteger32>(Instr->getSrc(2));
   // Only constant indices are allowed in PNaCl IR.
   assert(ElementIndex);
   unsigned Index = ElementIndex->getValue();
   assert(Index < typeNumElements(SourceVectNotLegalized->getType()));
 
   Type Ty = SourceVectNotLegalized->getType();
   Type ElementTy = typeElementType(Ty);
   Type InVectorElementTy = Traits::getInVectorElementType(Ty);
 
   if (ElementTy == IceType_i1) {
@@ skipping 1797 matching lines @@
 
   Operand *Condition = Select->getCondition();
   // Handle folding opportunities.
   if (const Inst *Producer = FoldingInfo.getProducerFor(Condition)) {
     assert(Producer->isDeleted());
     switch (BoolFolding<Traits>::getProducerKind(Producer)) {
     default:
       break;
     case BoolFolding<Traits>::PK_Icmp32:
     case BoolFolding<Traits>::PK_Icmp64: {
-      lowerIcmpAndConsumer(llvm::dyn_cast<InstIcmp>(Producer), Select);
+      lowerIcmpAndConsumer(llvm::cast<InstIcmp>(Producer), Select);
       return;
     }
     case BoolFolding<Traits>::PK_Fcmp: {
-      lowerFcmpAndConsumer(llvm::dyn_cast<InstFcmp>(Producer), Select);
+      lowerFcmpAndConsumer(llvm::cast<InstFcmp>(Producer), Select);
       return;
     }
     }
   }
 
   Operand *CmpResult = legalize(Condition, Legal_Reg | Legal_Mem);
   Operand *Zero = Ctx->getConstantZero(IceType_i32);
   _cmp(CmpResult, Zero);
   Operand *SrcT = Select->getTrueOperand();
   Operand *SrcF = Select->getFalseOperand();
@@ skipping 23 matching lines @@
   // instruction doesn't allow an immediate operand:
   // mov t, SrcT; cmov_!cond t, SrcF; mov dest, t
   if (llvm::isa<Constant>(SrcT) && !llvm::isa<Constant>(SrcF)) {
     std::swap(SrcT, SrcF);
     Cond = InstImpl<TraitsType>::InstX86Base::getOppositeCondition(Cond);
   }
   if (!Traits::Is64Bit && DestTy == IceType_i64) {
     SrcT = legalizeUndef(SrcT);
     SrcF = legalizeUndef(SrcF);
     // Set the low portion.
-    Variable *DestLo = llvm::cast<Variable>(loOperand(Dest));
+    auto *DestLo = llvm::cast<Variable>(loOperand(Dest));
     lowerSelectIntMove(DestLo, Cond, loOperand(SrcT), loOperand(SrcF));
     // Set the high portion.
-    Variable *DestHi = llvm::cast<Variable>(hiOperand(Dest));
+    auto *DestHi = llvm::cast<Variable>(hiOperand(Dest));
     lowerSelectIntMove(DestHi, Cond, hiOperand(SrcT), hiOperand(SrcF));
     return;
   }
 
   assert(DestTy == IceType_i16 || DestTy == IceType_i32 ||
          (Traits::Is64Bit && DestTy == IceType_i64));
   lowerSelectIntMove(Dest, Cond, SrcT, SrcF);
 }
 
 template <typename TraitsType>
@@ skipping 10 matching lines @@
 
 template <typename TraitsType>
 void TargetX86Base<TraitsType>::lowerMove(Variable *Dest, Operand *Src,
                                           bool IsRedefinition) {
   assert(Dest->getType() == Src->getType());
   assert(!Dest->isRematerializable());
   if (!Traits::Is64Bit && Dest->getType() == IceType_i64) {
     Src = legalize(Src);
     Operand *SrcLo = loOperand(Src);
     Operand *SrcHi = hiOperand(Src);
-    Variable *DestLo = llvm::cast<Variable>(loOperand(Dest));
-    Variable *DestHi = llvm::cast<Variable>(hiOperand(Dest));
+    auto *DestLo = llvm::cast<Variable>(loOperand(Dest));
+    auto *DestHi = llvm::cast<Variable>(hiOperand(Dest));
     Variable *T_Lo = nullptr, *T_Hi = nullptr;
     _mov(T_Lo, SrcLo);
     _redefined(_mov(DestLo, T_Lo), IsRedefinition);
     _mov(T_Hi, SrcHi);
     _redefined(_mov(DestHi, T_Hi), IsRedefinition);
   } else {
     Operand *SrcLegal;
     if (Dest->hasReg()) {
       // If Dest already has a physical register, then only basic legalization
       // is needed, as the source operand can be a register, immediate, or
@@ skipping 471 matching lines @@
   if (!RMW->isLastUse(RMW->getBeacon()))
     return;
   Operand *Src = RMW->getData();
   Type Ty = Src->getType();
   X86OperandMem *Addr = formMemoryOperand(RMW->getAddr(), Ty);
   doMockBoundsCheck(Addr);
   if (!Traits::Is64Bit && Ty == IceType_i64) {
     Src = legalizeUndef(Src);
     Operand *SrcLo = legalize(loOperand(Src), Legal_Reg | Legal_Imm);
     Operand *SrcHi = legalize(hiOperand(Src), Legal_Reg | Legal_Imm);
-    X86OperandMem *AddrLo = llvm::cast<X86OperandMem>(loOperand(Addr));
-    X86OperandMem *AddrHi = llvm::cast<X86OperandMem>(hiOperand(Addr));
+    auto *AddrLo = llvm::cast<X86OperandMem>(loOperand(Addr));
+    auto *AddrHi = llvm::cast<X86OperandMem>(hiOperand(Addr));
     switch (RMW->getOp()) {
     default:
       // TODO(stichnot): Implement other arithmetic operators.
       break;
     case InstArithmetic::Add:
       _add_rmw(AddrLo, SrcLo);
       _adc_rmw(AddrHi, SrcHi);
       return;
     case InstArithmetic::Sub:
       _sub_rmw(AddrLo, SrcLo);
@@ skipping 1292 matching lines @@
         emitGlobal(*Var, SectionSuffix);
       }
     }
   } break;
   }
 }
 } // end of namespace X86NAMESPACE
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASEIMPL_H