Subzero: Clean up some uses of *_cast<>.

src/IceTargetLoweringARM32.cpp

 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 118 matching lines @@
   CondARM32::Cond C1, C2;
 } TableIcmp64[] = {
 #define X(val, is_signed, swapped64, C_32, C1_64, C2_64)                       \
   { is_signed, swapped64, CondARM32::C1_64, CondARM32::C2_64 }                 \
   ,
     ICMPARM32_TABLE
 #undef X
 };
 
 CondARM32::Cond getIcmp32Mapping(InstIcmp::ICond Cond) {
-  size_t Index = static_cast<size_t>(Cond);
-  assert(Index < llvm::array_lengthof(TableIcmp32));
-  return TableIcmp32[Index].Mapping;
+  assert(Cond < llvm::array_lengthof(TableIcmp32));
+  return TableIcmp32[Cond].Mapping;
 }
 
 // In some cases, there are x-macros tables for both high-level and low-level
 // instructions/operands that use the same enum key value. The tables are kept
 // separate to maintain a proper separation between abstraction layers. There
 // is a risk that the tables could get out of sync if enum values are reordered
 // or if entries are added or deleted. The following anonymous namespaces use
 // static_asserts to ensure everything is kept in sync.
 
 // Validate the enum values in ICMPARM32_TABLE.
@@ skipping 3793 matching lines @@
   if (Cond.WhenTrue1 != CondARM32::kNone) {
     _mov_redefined(T, _1, Cond.WhenTrue1);
   }
 
   _mov(Dest, T);
 }
 
 TargetARM32::CondWhenTrue
 TargetARM32::lowerInt64IcmpCond(InstIcmp::ICond Condition, Operand *Src0,
                                 Operand *Src1) {
-  size_t Index = static_cast<size_t>(Condition);
-  assert(Index < llvm::array_lengthof(TableIcmp64));
+  assert(Condition < llvm::array_lengthof(TableIcmp64));
 
   Int32Operands SrcsLo(loOperand(Src0), loOperand(Src1));
   Int32Operands SrcsHi(hiOperand(Src0), hiOperand(Src1));
   assert(SrcsLo.hasConstOperand() == SrcsHi.hasConstOperand());
   assert(SrcsLo.swappedOperands() == SrcsHi.swappedOperands());
 
   if (SrcsLo.hasConstOperand()) {
     const uint32_t ValueLo = SrcsLo.getConstantValue();
     const uint32_t ValueHi = SrcsHi.getConstantValue();
     const uint64_t Value = (static_cast<uint64_t>(ValueHi) << 32) | ValueLo;
     if ((Condition == InstIcmp::Eq || Condition == InstIcmp::Ne) &&
         Value == 0) {
       Variable *T = makeReg(IceType_i32);
       Variable *Src0LoR = SrcsLo.src0R(this);
       Variable *Src0HiR = SrcsHi.src0R(this);
       _orrs(T, Src0LoR, Src0HiR);
       Context.insert<InstFakeUse>(T);
-      return CondWhenTrue(TableIcmp64[Index].C1);
+      return CondWhenTrue(TableIcmp64[Condition].C1);
     }
 
     Variable *Src0RLo = SrcsLo.src0R(this);
     Variable *Src0RHi = SrcsHi.src0R(this);
     Operand *Src1RFLo = SrcsLo.src1RF(this);
     Operand *Src1RFHi = ValueLo == ValueHi ? Src1RFLo : SrcsHi.src1RF(this);
 
-    const bool UseRsb = TableIcmp64[Index].Swapped != SrcsLo.swappedOperands();
+    const bool UseRsb =
+        TableIcmp64[Condition].Swapped != SrcsLo.swappedOperands();
 
     if (UseRsb) {
-      if (TableIcmp64[Index].IsSigned) {
+      if (TableIcmp64[Condition].IsSigned) {
         Variable *T = makeReg(IceType_i32);
         _rsbs(T, Src0RLo, Src1RFLo);
         Context.insert<InstFakeUse>(T);
 
         T = makeReg(IceType_i32);
         _rscs(T, Src0RHi, Src1RFHi);
         // We need to add a FakeUse here because liveness gets mad at us (Def
         // without Use.) Note that flag-setting instructions are considered to
         // have side effects and, therefore, are not DCE'ed.
         Context.insert<InstFakeUse>(T);
       } else {
         Variable *T = makeReg(IceType_i32);
         _rsbs(T, Src0RHi, Src1RFHi);
         Context.insert<InstFakeUse>(T);
 
         T = makeReg(IceType_i32);
         _rsbs(T, Src0RLo, Src1RFLo, CondARM32::EQ);
         Context.insert<InstFakeUse>(T);
       }
     } else {
-      if (TableIcmp64[Index].IsSigned) {
+      if (TableIcmp64[Condition].IsSigned) {
         _cmp(Src0RLo, Src1RFLo);
         Variable *T = makeReg(IceType_i32);
         _sbcs(T, Src0RHi, Src1RFHi);
         Context.insert<InstFakeUse>(T);
       } else {
         _cmp(Src0RHi, Src1RFHi);
         _cmp(Src0RLo, Src1RFLo, CondARM32::EQ);
       }
     }
 
-    return CondWhenTrue(TableIcmp64[Index].C1);
+    return CondWhenTrue(TableIcmp64[Condition].C1);
   }
 
   Variable *Src0RLo, *Src0RHi;
   Operand *Src1RFLo, *Src1RFHi;
-  if (TableIcmp64[Index].Swapped) {
+  if (TableIcmp64[Condition].Swapped) {
     Src0RLo = legalizeToReg(loOperand(Src1));
     Src0RHi = legalizeToReg(hiOperand(Src1));
     Src1RFLo = legalizeToReg(loOperand(Src0));
     Src1RFHi = legalizeToReg(hiOperand(Src0));
   } else {
     Src0RLo = legalizeToReg(loOperand(Src0));
     Src0RHi = legalizeToReg(hiOperand(Src0));
     Src1RFLo = legalizeToReg(loOperand(Src1));
     Src1RFHi = legalizeToReg(hiOperand(Src1));
   }
@@ skipping 20 matching lines @@
   // that's nice in that it's just as short but has fewer dependencies for
   // better ILP at the cost of more registers.
   //
   // Otherwise for signed/unsigned <, <=, etc. LLVM uses a sequence with two
   // unconditional mov #0, two cmps, two conditional mov #1, and one
   // conditional reg mov. That has few dependencies for good ILP, but is a
   // longer sequence.
   //
   // So, we are going with the GCC version since it's usually better (except
   // perhaps for eq/ne). We could revisit special-casing eq/ne later.
-  if (TableIcmp64[Index].IsSigned) {
+  if (TableIcmp64[Condition].IsSigned) {
     Variable *ScratchReg = makeReg(IceType_i32);
     _cmp(Src0RLo, Src1RFLo);
     _sbcs(ScratchReg, Src0RHi, Src1RFHi);
     // ScratchReg isn't going to be used, but we need the side-effect of
     // setting flags from this operation.
     Context.insert<InstFakeUse>(ScratchReg);
   } else {
     _cmp(Src0RHi, Src1RFHi);
     _cmp(Src0RLo, Src1RFLo, CondARM32::EQ);
   }
-  return CondWhenTrue(TableIcmp64[Index].C1);
+  return CondWhenTrue(TableIcmp64[Condition].C1);
 }
 
 TargetARM32::CondWhenTrue
 TargetARM32::lowerInt32IcmpCond(InstIcmp::ICond Condition, Operand *Src0,
                                 Operand *Src1) {
   Int32Operands Srcs(Src0, Src1);
   if (!Srcs.hasConstOperand()) {
 
     Variable *Src0R = Srcs.src0R(this);
     Operand *Src1RF = Srcs.src1RF(this);
@@ skipping 2439 matching lines @@
   Str << ".eabi_attribute 14, 3   @ Tag_ABI_PCS_R9_use: Not used\n";
 }
 
 llvm::SmallBitVector TargetARM32::TypeToRegisterSet[RegARM32::RCARM32_NUM];
 llvm::SmallBitVector
     TargetARM32::TypeToRegisterSetUnfiltered[RegARM32::RCARM32_NUM];
 llvm::SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM];
 
 } // end of namespace ARM32
 } // end of namespace Ice