Add NOP to ARM IR lowering.

src/IceInstARM32.cpp

 //===- subzero/src/IceInstARM32.cpp - ARM32 instruction implementation ----===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 1203 matching lines @@
 }
 
 template <> void InstARM32Tst::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 2);
   auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
   Asm->tst(getSrc(0), getSrc(1), getPredicate());
   if (Asm->needsTextFixup())
     emitUsingTextFixup(Func);
 }
 
+InstARM32Dmb::InstARM32Dmb(Cfg *Func)
+    : InstARM32Pred(Func, InstARM32::Dmb, 0, nullptr, CondARM32::AL) {}
+
+InstARM32Nop::InstARM32Nop(Cfg *Func)
+    : InstARM32Pred(Func, InstARM32::Nop, 0, nullptr, CondARM32::AL) {}
+
 InstARM32Vcmp::InstARM32Vcmp(Cfg *Func, Variable *Src0, Operand *Src1,
                              CondARM32::Cond Predicate)
     : InstARM32Pred(Func, InstARM32::Vcmp, 2, nullptr, Predicate) {
   HasSideEffects = true;
   addSource(Src0);
   addSource(Src1);
 }
 
 InstARM32Vmrs::InstARM32Vmrs(Cfg *Func, CondARM32::Cond Predicate)
     : InstARM32Pred(Func, InstARM32::Vmrs, 0, nullptr, Predicate) {
   HasSideEffects = true;
 }
 
 InstARM32Vabs::InstARM32Vabs(Cfg *Func, Variable *Dest, Variable *Src,
                              CondARM32::Cond Predicate)
     : InstARM32Pred(Func, InstARM32::Vabs, 1, Dest, Predicate) {
   addSource(Src);
 }
 
-InstARM32Dmb::InstARM32Dmb(Cfg *Func)
-    : InstARM32Pred(Func, InstARM32::Dmb, 0, nullptr, CondARM32::AL) {}
-
 // ======================== Dump routines ======================== //
 
 // Two-addr ops
 template <> const char *InstARM32Movt::Opcode = "movt";
 // Unary ops
 template <> const char *InstARM32Movw::Opcode = "movw";
 template <> const char *InstARM32Clz::Opcode = "clz";
 template <> const char *InstARM32Mvn::Opcode = "mvn";
 template <> const char *InstARM32Rbit::Opcode = "rbit";
 template <> const char *InstARM32Rev::Opcode = "rev";
@@ skipping 1184 matching lines @@
     emitUsingTextFixup(Func);
 }
 
 void InstARM32Dmb::dump(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Func->getContext()->getStrDump() << "dmb\t"
                                       "sy";
 }
 
+void InstARM32Nop::emit(const Cfg *Func) const {
+  if (!BuildDefs::dump())
+    return;
+  assert(getSrcSize() == 0);
+  Func->getContext()->getStrEmit() << "\t"
+                                   << "nop";
+}
+
+void InstARM32Nop::emitIAS(const Cfg *Func) const {
+  assert(getSrcSize() == 0);
+  Func->getAssembler<ARM32::AssemblerARM32>()->nop();
+}
+
+void InstARM32Nop::dump(const Cfg *Func) const {
+  if (!BuildDefs::dump())
+    return;
+  assert(getSrcSize() == 0);
+  Func->getContext()->getStrDump() << "nop";
+}
+
 void OperandARM32Mem::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   Str << "[";
   getBase()->emit(Func);
   switch (getAddrMode()) {
   case PostIndex:
   case NegPostIndex:
     Str << "]";
@@ skipping 230 matching lines @@
 
 template class InstARM32FourAddrGPR<InstARM32::Mla>;
 template class InstARM32FourAddrGPR<InstARM32::Mls>;
 
 template class InstARM32CmpLike<InstARM32::Cmn>;
 template class InstARM32CmpLike<InstARM32::Cmp>;
 template class InstARM32CmpLike<InstARM32::Tst>;
 
 } // end of namespace ARM32
 } // end of namespace Ice