Fix ARM assembler to pop registers in reverse order of pushes.

src/IceInstARM32.h

 //===- subzero/src/IceInstARM32.h - ARM32 machine instructions --*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 1084 matching lines @@
   virtual const char *getGPROpcode() const = 0;
   virtual const char *getSRegOpcode() const = 0;
   virtual Variable *getStackReg(SizeT Index) const = 0;
   virtual SizeT getNumStackRegs() const = 0;
   virtual void emitSingleGPR(const Cfg *Func, const EmitForm Form,
                              const Variable *Reg) const = 0;
   virtual void emitMultipleGPRs(const Cfg *Func, const EmitForm Form,
                                 IValueT Registers) const = 0;
   virtual void emitSRegs(const Cfg *Func, const EmitForm Form,
                          const Variable *BaseReg, SizeT RegCount) const = 0;
+  // The following are for accessing S registers, which must be popped in
+  // the reverse order they are pushed.
+  virtual bool isAssignedConsecutiveRegisters(const Variable *Before,
+                                              const Variable *After) const = 0;
+  virtual Variable *getStackSReg(SizeT Index, SizeT Size) const = 0;
+  virtual const Variable *updateBaseReg(const Variable *BaseReg,
+                                        const Variable *NextReg) const = 0;
 };
 
 /// Pops a list of registers. It may be a list of GPRs, or a list of VFP "s"
 /// regs, but not both. In any case, the list must be sorted.
 class InstARM32Pop : public InstARM32RegisterStackOp {
   InstARM32Pop() = delete;
   InstARM32Pop(const InstARM32Pop &) = delete;
   InstARM32Pop &operator=(const InstARM32Pop &) = delete;
 
 public:
   static InstARM32Pop *create(Cfg *Func, const VarList &Dests) {
     return new (Func->allocate<InstARM32Pop>()) InstARM32Pop(Func, Dests);
   }
   static bool classof(const Inst *Inst) { return isClassof(Inst, Pop); }
 
 private:
   InstARM32Pop(Cfg *Func, const VarList &Dests);
   virtual const char *getGPROpcode() const final;
   virtual const char *getSRegOpcode() const final;
   Variable *getStackReg(SizeT Index) const final;
   SizeT getNumStackRegs() const final;
   void emitSingleGPR(const Cfg *Func, const EmitForm Form,
                      const Variable *Reg) const final;
   void emitMultipleGPRs(const Cfg *Func, const EmitForm Form,
                         IValueT Registers) const final;
   void emitSRegs(const Cfg *Func, const EmitForm Form, const Variable *BaseReg,
                  SizeT RegCount) const final;
-
+  bool isAssignedConsecutiveRegisters(const Variable *Before,
+                                      const Variable *After) const final;
+  Variable *getStackSReg(SizeT Index, SizeT Size) const final;
+  const Variable *updateBaseReg(const Variable *BaseReg,
+                                const Variable *NextReg) const final;
   VarList Dests;

[John, 2016/02/05 01:46:25]

For future reference: you could have marked the class final instead. But please
do not change it. :)

[Karl, 2016/02/05 17:00:05]

Acknowledged.

 };
 
 /// Pushes a list of registers. Just like Pop (see above), the list may be of
 /// GPRs, or VFP "s" registers, but not both.
 class InstARM32Push : public InstARM32RegisterStackOp {
   InstARM32Push() = delete;
   InstARM32Push(const InstARM32Push &) = delete;
   InstARM32Push &operator=(const InstARM32Push &) = delete;
 
 public:
   static InstARM32Push *create(Cfg *Func, const VarList &Srcs) {
     return new (Func->allocate<InstARM32Push>()) InstARM32Push(Func, Srcs);
   }
   static bool classof(const Inst *Inst) { return isClassof(Inst, Push); }
 
 private:
   InstARM32Push(Cfg *Func, const VarList &Srcs);
   const char *getGPROpcode() const final;
   const char *getSRegOpcode() const final;
   Variable *getStackReg(SizeT Index) const final;
   SizeT getNumStackRegs() const final;
   void emitSingleGPR(const Cfg *Func, const EmitForm Form,
                      const Variable *Reg) const final;
   void emitMultipleGPRs(const Cfg *Func, const EmitForm Form,
                         IValueT Registers) const final;
   void emitSRegs(const Cfg *Func, const EmitForm Form, const Variable *BaseReg,
                  SizeT RegCount) const final;
+  bool isAssignedConsecutiveRegisters(const Variable *Before,
+                                      const Variable *After) const final;
+  Variable *getStackSReg(SizeT Index, SizeT Size) const final;
+  const Variable *updateBaseReg(const Variable *BaseReg,
+                                const Variable *NextReg) const final;
 };
 
 /// Ret pseudo-instruction. This is actually a "bx" instruction with an "lr"
 /// register operand, but epilogue lowering will search for a Ret instead of a
 /// generic "bx". This instruction also takes a Source operand (for non-void
 /// returning functions) for liveness analysis, though a FakeUse before the ret
 /// would do just as well.
 ///
 /// NOTE: Even though "bx" can be predicated, for now leave out the predication
 /// since it's not yet known to be useful for Ret. That may complicate finding
@@ skipping 273 matching lines @@
 // violations and link errors.
 
 template <> void InstARM32Ldr::emit(const Cfg *Func) const;
 template <> void InstARM32Movw::emit(const Cfg *Func) const;
 template <> void InstARM32Movt::emit(const Cfg *Func) const;
 
 } // end of namespace ARM32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEINSTARM32_H