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Issue 16695007: Fix decoding of object pool access in code patching on ARM. (Closed) Base URL: http://dart.googlecode.com/svn/branches/bleeding_edge/dart/
Patch Set: Created 7 years, 6 months ago
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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #include "vm/globals.h" // Needed here to get TARGET_ARCH_ARM. 5 #include "vm/globals.h" // Needed here to get TARGET_ARCH_ARM.
6 #if defined(TARGET_ARCH_ARM) 6 #if defined(TARGET_ARCH_ARM)
7 7
8 #include "vm/constants_arm.h" 8 #include "vm/constants_arm.h"
9 #include "vm/cpu.h" 9 #include "vm/cpu.h"
10 #include "vm/instructions.h" 10 #include "vm/instructions.h"
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86 uword instr = Back(++end); 86 uword instr = Back(++end);
87 int offset = 0; 87 int offset = 0;
88 if ((instr & 0xffff0000) == 0xe59a0000) { // ldr reg, [pp, #+offset] 88 if ((instr & 0xffff0000) == 0xe59a0000) { // ldr reg, [pp, #+offset]
89 offset = instr & 0xfff; 89 offset = instr & 0xfff;
90 *reg = static_cast<Register>((instr & 0xf000) >> 12); 90 *reg = static_cast<Register>((instr & 0xf000) >> 12);
91 } else { 91 } else {
92 ASSERT((instr & 0xfff00000) == 0xe5900000); // ldr reg, [reg, #+offset] 92 ASSERT((instr & 0xfff00000) == 0xe5900000); // ldr reg, [reg, #+offset]
93 offset = instr & 0xfff; 93 offset = instr & 0xfff;
94 instr = Back(++end); 94 instr = Back(++end);
95 if ((instr & 0xffff0000) == 0xe28a0000) { // add reg, pp, shifter_op 95 if ((instr & 0xffff0000) == 0xe28a0000) { // add reg, pp, shifter_op
96 const int rot = (instr & 0xf00) * 2; 96 const int rot = (instr & 0xf00) >> 7;
97 const int imm8 = instr & 0xff; 97 const int imm8 = instr & 0xff;
98 offset |= (imm8 >> rot) | (imm8 << (32 - rot)); 98 offset += (imm8 >> rot) | (imm8 << (32 - rot));
99 *reg = static_cast<Register>((instr & 0xf000) >> 12); 99 *reg = static_cast<Register>((instr & 0xf000) >> 12);
100 } else { 100 } else {
101 ASSERT((instr & 0xffff0000) == 0xe08a0000); // add reg, pp, reg 101 ASSERT((instr & 0xffff0000) == 0xe08a0000); // add reg, pp, reg
102 end = DecodeLoadWordImmediate(end, reg, &offset); 102 end = DecodeLoadWordImmediate(end, reg, &offset);
103 } 103 }
104 } 104 }
105 offset += kHeapObjectTag; 105 offset += kHeapObjectTag;
106 ASSERT(Utils::IsAligned(offset, 4)); 106 ASSERT(Utils::IsAligned(offset, 4));
107 *index = (offset - Array::data_offset())/4; 107 *index = (offset - Array::data_offset())/4;
108 return end; 108 return end;
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192 uword movt_ip = 0xe340c000 | ((target_hi >> 12) << 16) | (target_hi & 0xfff); 192 uword movt_ip = 0xe340c000 | ((target_hi >> 12) << 16) | (target_hi & 0xfff);
193 *reinterpret_cast<uword*>(pc_ + (0 * Instr::kInstrSize)) = movw_ip; 193 *reinterpret_cast<uword*>(pc_ + (0 * Instr::kInstrSize)) = movw_ip;
194 *reinterpret_cast<uword*>(pc_ + (1 * Instr::kInstrSize)) = movt_ip; 194 *reinterpret_cast<uword*>(pc_ + (1 * Instr::kInstrSize)) = movt_ip;
195 CPU::FlushICache(pc_, 2 * Instr::kInstrSize); 195 CPU::FlushICache(pc_, 2 * Instr::kInstrSize);
196 } 196 }
197 197
198 } // namespace dart 198 } // namespace dart
199 199
200 #endif // defined TARGET_ARCH_ARM 200 #endif // defined TARGET_ARCH_ARM
201 201
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