Subzero. Uses fixups to calculate addend to relocations.

src/IceAssemblerARM32.h

 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 28 matching lines @@
 namespace ARM32 {
 
 /// Handles encoding of bottom/top 16 bits of an address using movw/movt.
 class MoveRelocatableFixup final : public AssemblerFixup {
   MoveRelocatableFixup &operator=(const MoveRelocatableFixup &) = delete;
   MoveRelocatableFixup(const MoveRelocatableFixup &) = default;
 
 public:
   MoveRelocatableFixup() = default;
   size_t emit(GlobalContext *Ctx, const Assembler &Asm) const final;
+  void emitOffset(Assembler *Asm) const;
 };
 
 /// Handles encoding of branch and link to global location.
 class BlRelocatableFixup final : public AssemblerFixup {
   BlRelocatableFixup(const BlRelocatableFixup &) = delete;
   BlRelocatableFixup &operator=(const BlRelocatableFixup &) = delete;
 
 public:
   BlRelocatableFixup() = default;
   size_t emit(GlobalContext *Ctx, const Assembler &Asm) const final;
+  void emitOffset(Assembler *Asm) const;
 };
 
 class AssemblerARM32 : public Assembler {
   AssemblerARM32(const AssemblerARM32 &) = delete;
   AssemblerARM32 &operator=(const AssemblerARM32 &) = delete;
 
 public:
   // Rotation values.
   enum RotationValue {
     kRotateNone, // Omitted
@@ skipping 560 matching lines @@
                    const char *OpcodeName);
 
   // Pattern cccctttxxxxnnnn0000iiiiiiiiiiii where cccc=Cond, nnnn=Rn,
   // ttt=Instruction type (derived from OpSrc1), iiiiiiiiiiii is derived from
   // OpSrc1, and xxxx=Opcode.
   void emitCompareOp(CondARM32::Cond Cond, IValueT Opcode, const Operand *OpRn,
                      const Operand *OpSrc1, const char *CmpName);
 
   void emitBranch(Label *L, CondARM32::Cond, bool Link);
 
-  // Encodes the given Offset into the branch instruction Inst.
-  IValueT encodeBranchOffset(IOffsetT Offset, IValueT Inst);
-
   // Returns the offset encoded in the branch instruction Inst.
   static IOffsetT decodeBranchOffset(IValueT Inst);
 
   // Implements movw/movt, generating pattern ccccxxxxxxxsiiiiddddiiiiiiiiiiii
   // where cccc=Cond, xxxxxxx<<21=Opcode, dddd=Rd, s=SetFlags, and
   // iiiiiiiiiiiiiiii=Imm16.
   void emitMovwt(CondARM32::Cond Cond, bool IsMovw, const Operand *OpRd,
                  const Operand *OpSrc, const char *MovName);
 
   // Emit VFP instruction with 3 D registers.
@@ skipping 10 matching lines @@
 
   void emitVFPsss(CondARM32::Cond Cond, IValueT Opcode, const Operand *OpSd,
                   const Operand *OpSn, const Operand *OpSm,
                   const char *InstName);
 };
 
 } // end of namespace ARM32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H