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1 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===// | 1 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===// |
2 // | 2 // |
3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file | 3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file |
4 // for details. All rights reserved. Use of this source code is governed by a | 4 // for details. All rights reserved. Use of this source code is governed by a |
5 // BSD-style license that can be found in the LICENSE file. | 5 // BSD-style license that can be found in the LICENSE file. |
6 // | 6 // |
7 // Modified by the Subzero authors. | 7 // Modified by the Subzero authors. |
8 // | 8 // |
9 //===----------------------------------------------------------------------===// | 9 //===----------------------------------------------------------------------===// |
10 // | 10 // |
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39 namespace ARM32 { | 39 namespace ARM32 { |
40 | 40 |
41 /// Handles encoding of bottom/top 16 bits of an address using movw/movt. | 41 /// Handles encoding of bottom/top 16 bits of an address using movw/movt. |
42 class MoveRelocatableFixup final : public AssemblerFixup { | 42 class MoveRelocatableFixup final : public AssemblerFixup { |
43 MoveRelocatableFixup &operator=(const MoveRelocatableFixup &) = delete; | 43 MoveRelocatableFixup &operator=(const MoveRelocatableFixup &) = delete; |
44 MoveRelocatableFixup(const MoveRelocatableFixup &) = default; | 44 MoveRelocatableFixup(const MoveRelocatableFixup &) = default; |
45 | 45 |
46 public: | 46 public: |
47 MoveRelocatableFixup() = default; | 47 MoveRelocatableFixup() = default; |
48 size_t emit(GlobalContext *Ctx, const Assembler &Asm) const final; | 48 size_t emit(GlobalContext *Ctx, const Assembler &Asm) const final; |
| 49 void emitOffset(Assembler *Asm) const; |
49 }; | 50 }; |
50 | 51 |
51 /// Handles encoding of branch and link to global location. | 52 /// Handles encoding of branch and link to global location. |
52 class BlRelocatableFixup final : public AssemblerFixup { | 53 class BlRelocatableFixup final : public AssemblerFixup { |
53 BlRelocatableFixup(const BlRelocatableFixup &) = delete; | 54 BlRelocatableFixup(const BlRelocatableFixup &) = delete; |
54 BlRelocatableFixup &operator=(const BlRelocatableFixup &) = delete; | 55 BlRelocatableFixup &operator=(const BlRelocatableFixup &) = delete; |
55 | 56 |
56 public: | 57 public: |
57 BlRelocatableFixup() = default; | 58 BlRelocatableFixup() = default; |
58 size_t emit(GlobalContext *Ctx, const Assembler &Asm) const final; | 59 size_t emit(GlobalContext *Ctx, const Assembler &Asm) const final; |
| 60 void emitOffset(Assembler *Asm) const; |
59 }; | 61 }; |
60 | 62 |
61 class AssemblerARM32 : public Assembler { | 63 class AssemblerARM32 : public Assembler { |
62 AssemblerARM32(const AssemblerARM32 &) = delete; | 64 AssemblerARM32(const AssemblerARM32 &) = delete; |
63 AssemblerARM32 &operator=(const AssemblerARM32 &) = delete; | 65 AssemblerARM32 &operator=(const AssemblerARM32 &) = delete; |
64 | 66 |
65 public: | 67 public: |
66 // Rotation values. | 68 // Rotation values. |
67 enum RotationValue { | 69 enum RotationValue { |
68 kRotateNone, // Omitted | 70 kRotateNone, // Omitted |
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629 const char *OpcodeName); | 631 const char *OpcodeName); |
630 | 632 |
631 // Pattern cccctttxxxxnnnn0000iiiiiiiiiiii where cccc=Cond, nnnn=Rn, | 633 // Pattern cccctttxxxxnnnn0000iiiiiiiiiiii where cccc=Cond, nnnn=Rn, |
632 // ttt=Instruction type (derived from OpSrc1), iiiiiiiiiiii is derived from | 634 // ttt=Instruction type (derived from OpSrc1), iiiiiiiiiiii is derived from |
633 // OpSrc1, and xxxx=Opcode. | 635 // OpSrc1, and xxxx=Opcode. |
634 void emitCompareOp(CondARM32::Cond Cond, IValueT Opcode, const Operand *OpRn, | 636 void emitCompareOp(CondARM32::Cond Cond, IValueT Opcode, const Operand *OpRn, |
635 const Operand *OpSrc1, const char *CmpName); | 637 const Operand *OpSrc1, const char *CmpName); |
636 | 638 |
637 void emitBranch(Label *L, CondARM32::Cond, bool Link); | 639 void emitBranch(Label *L, CondARM32::Cond, bool Link); |
638 | 640 |
639 // Encodes the given Offset into the branch instruction Inst. | |
640 IValueT encodeBranchOffset(IOffsetT Offset, IValueT Inst); | |
641 | |
642 // Returns the offset encoded in the branch instruction Inst. | 641 // Returns the offset encoded in the branch instruction Inst. |
643 static IOffsetT decodeBranchOffset(IValueT Inst); | 642 static IOffsetT decodeBranchOffset(IValueT Inst); |
644 | 643 |
645 // Implements movw/movt, generating pattern ccccxxxxxxxsiiiiddddiiiiiiiiiiii | 644 // Implements movw/movt, generating pattern ccccxxxxxxxsiiiiddddiiiiiiiiiiii |
646 // where cccc=Cond, xxxxxxx<<21=Opcode, dddd=Rd, s=SetFlags, and | 645 // where cccc=Cond, xxxxxxx<<21=Opcode, dddd=Rd, s=SetFlags, and |
647 // iiiiiiiiiiiiiiii=Imm16. | 646 // iiiiiiiiiiiiiiii=Imm16. |
648 void emitMovwt(CondARM32::Cond Cond, bool IsMovw, const Operand *OpRd, | 647 void emitMovwt(CondARM32::Cond Cond, bool IsMovw, const Operand *OpRd, |
649 const Operand *OpSrc, const char *MovName); | 648 const Operand *OpSrc, const char *MovName); |
650 | 649 |
651 // Emit VFP instruction with 3 D registers. | 650 // Emit VFP instruction with 3 D registers. |
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662 | 661 |
663 void emitVFPsss(CondARM32::Cond Cond, IValueT Opcode, const Operand *OpSd, | 662 void emitVFPsss(CondARM32::Cond Cond, IValueT Opcode, const Operand *OpSd, |
664 const Operand *OpSn, const Operand *OpSm, | 663 const Operand *OpSn, const Operand *OpSm, |
665 const char *InstName); | 664 const char *InstName); |
666 }; | 665 }; |
667 | 666 |
668 } // end of namespace ARM32 | 667 } // end of namespace ARM32 |
669 } // end of namespace Ice | 668 } // end of namespace Ice |
670 | 669 |
671 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H | 670 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H |
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