Subzero. Uses fixups to calculate addend to relocations.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 488 matching lines @@
   }
   return CantEncode;
 }
 
 // Checks that Offset can fit in imm24 constant of branch (b) instruction.
 bool canEncodeBranchOffset(IOffsetT Offset) {
   return Utils::IsAligned(Offset, 4) &&
          Utils::IsInt(kBranchOffsetBits, Offset >> 2);
 }
 
+IValueT encodeBranchOffset(IOffsetT Offset, IValueT Inst) {
+  // Adjust offset to the way ARM CPUs read PC.
+  Offset -= kPCReadOffset;
+
+  bool IsGoodOffset = canEncodeBranchOffset(Offset);

[Jim Stichnoth, 2016/02/03 23:18:27]

Maybe just:
  assert(canEncodeBranchOffset(Offset));

[John, 2016/02/04 18:28:50]

Done.

+  assert(IsGoodOffset);
+  (void)IsGoodOffset;
+
+  // Properly preserve only the bits supported in the instruction.
+  Offset >>= 2;
+  Offset &= kBranchOffsetMask;
+  return (Inst & ~kBranchOffsetMask) | Offset;
+}
+
 IValueT encodeRegister(const Operand *OpReg, RegSetWanted WantedRegSet,
                        const char *RegName, const char *InstName) {
   IValueT Reg = 0;
   if (encodeOperand(OpReg, Reg, WantedRegSet) != EncodedAsRegister)
     llvm::report_fatal_error(std::string(InstName) + ": Can't find register " +
                              RegName);
   return Reg;
 }
 
 IValueT encodeGPRegister(const Operand *OpReg, const char *RegName,
@@ skipping 69 matching lines @@
   IValueT Inst = Asm.load<IValueT>(position());
   Str << "\t"
          "mov" << (kind() == llvm::ELF::R_ARM_MOVW_ABS_NC ? "w" : "t") << "\t"
       << RegARM32::getRegName((Inst >> kRdShift) & 0xF)
       << ", #:" << (kind() == llvm::ELF::R_ARM_MOVW_ABS_NC ? "lower" : "upper")
       << "16:" << symbol(Ctx, &Asm) << "\t@ .word "
       << llvm::format_hex_no_prefix(Inst, 8) << "\n";
   return InstARM32::InstSize;
 }
 
+// This fixup points to an ARM32 instruction with the following format:
+void MoveRelocatableFixup::emitOffset(Assembler *Asm) const {
+  // cccc00110T00iiiiddddiiiiiiiiiiii where cccc=Cond, dddd=Rd,
+  // iiiiiiiiiiiiiiii = Imm16, and T=1 for movt.
+
+  const IValueT Inst = Asm->load<IValueT>(position());
+  constexpr IValueT Imm16Mask = 0x000F0FFF;
+  const IValueT Imm16 =
+      offset() >> (kind() == llvm::ELF::R_ARM_MOVW_ABS_NC ? 0 : 16) & 0xffff;
+  Asm->store(position(),
+             (Inst & ~Imm16Mask) | ((Imm16 >> 12) << 16) | (Imm16 & 0xfff));
+}
+
 MoveRelocatableFixup *AssemblerARM32::createMoveFixup(bool IsMovW,
                                                       const Constant *Value) {
   MoveRelocatableFixup *F =
       new (allocate<MoveRelocatableFixup>()) MoveRelocatableFixup();
   F->set_kind(IsMovW ? llvm::ELF::R_ARM_MOVW_ABS_NC
                      : llvm::ELF::R_ARM_MOVT_ABS);
   F->set_value(Value);
   Buffer.installFixup(F);
   return F;
 }
 
 size_t BlRelocatableFixup::emit(GlobalContext *Ctx,
                                 const Assembler &Asm) const {
   if (!BuildDefs::dump())
     return InstARM32::InstSize;
   Ostream &Str = Ctx->getStrEmit();
   IValueT Inst = Asm.load<IValueT>(position());
   Str << "\t"
          "bl\t" << symbol(Ctx, &Asm) << "\t@ .word "
       << llvm::format_hex_no_prefix(Inst, 8) << "\n";
   return InstARM32::InstSize;
 }
 
+void BlRelocatableFixup::emitOffset(Assembler *Asm) const {
+  // cccc101liiiiiiiiiiiiiiiiiiiiiiii where cccc=Cond, l=Link, and
+  // iiiiiiiiiiiiiiiiiiiiiiii=
+  // EncodedBranchOffset(cccc101l000000000000000000000000, Offset);
+  const IValueT Inst = Asm->load<IValueT>(position());
+  constexpr IValueT OffsetMask = 0x00FFFFFF;
+  Asm->store(position(), encodeBranchOffset(offset(), Inst & ~OffsetMask));
+}
+
 void AssemblerARM32::padWithNop(intptr_t Padding) {
   constexpr intptr_t InstWidth = sizeof(IValueT);
   assert(Padding % InstWidth == 0 &&
          "Padding not multiple of instruction size");
   for (intptr_t i = 0; i < Padding; i += InstWidth)
     nop();
 }
 
 BlRelocatableFixup *
 AssemblerARM32::createBlFixup(const ConstantRelocatable *BlTarget) {
@@ skipping 29 matching lines @@
     Labels.resize(Number + 1);
   }
   L = Labels[Number];
   if (!L) {
     L = new (this->allocate<Label>()) Label();
     Labels[Number] = L;
   }
   return L;
 }
 
-IValueT AssemblerARM32::encodeBranchOffset(IOffsetT Offset, IValueT Inst) {
-  // Adjust offset to the way ARM CPUs read PC.
-  Offset -= kPCReadOffset;
-
-  bool IsGoodOffset = canEncodeBranchOffset(Offset);
-  assert(IsGoodOffset);
-  (void)IsGoodOffset;
-
-  // Properly preserve only the bits supported in the instruction.
-  Offset >>= 2;
-  Offset &= kBranchOffsetMask;
-  return (Inst & ~kBranchOffsetMask) | Offset;
-}
-
 // Pull out offset from branch Inst.
 IOffsetT AssemblerARM32::decodeBranchOffset(IValueT Inst) {
   // Sign-extend, left-shift by 2, and adjust to the way ARM CPUs read PC.
   IOffsetT Offset = static_cast<IOffsetT>((Inst & kBranchOffsetMask) << 8);
   return (Offset >> 6) + kPCReadOffset;
 }
 
 void AssemblerARM32::bind(Label *L) {
   IOffsetT BoundPc = Buffer.size();
   assert(!L->isBound()); // Labels can only be bound once.
@@ skipping 2227 matching lines @@
   constexpr const char *Vsqrts = "vsqrts";
   IValueT Sd = encodeSRegister(OpSd, "Sd", Vsqrts);
   IValueT Sm = encodeSRegister(OpSm, "Sm", Vsqrts);
   constexpr IValueT VsqrtsOpcode = B23 | B21 | B20 | B16 | B7 | B6;
   constexpr IValueT S0 = 0;
   emitVFPsss(Cond, VsqrtsOpcode, Sd, S0, Sm);
 }
 
 } // end of namespace ARM32
 } // end of namespace Ice