Chromium Code Reviews| OLD | NEW |
|---|---|
| 1 //===- subzero/src/IceTargetLoweringMIPS32.cpp - MIPS32 lowering ----------===// | 1 //===- subzero/src/IceTargetLoweringMIPS32.cpp - MIPS32 lowering ----------===// |
| 2 // | 2 // |
| 3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
| 4 // | 4 // |
| 5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
| 6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
| 7 // | 7 // |
| 8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
| 9 /// | 9 /// |
| 10 /// \file | 10 /// \file |
| (...skipping 253 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... | |
| 264 if (Func->hasError()) | 264 if (Func->hasError()) |
| 265 return; | 265 return; |
| 266 Func->dump("After stack frame mapping"); | 266 Func->dump("After stack frame mapping"); |
| 267 | 267 |
| 268 // Nop insertion | 268 // Nop insertion |
| 269 if (Ctx->getFlags().shouldDoNopInsertion()) { | 269 if (Ctx->getFlags().shouldDoNopInsertion()) { |
| 270 Func->doNopInsertion(); | 270 Func->doNopInsertion(); |
| 271 } | 271 } |
| 272 } | 272 } |
| 273 | 273 |
| 274 bool TargetMIPS32::doBranchOpt(Inst *I, const CfgNode *NextNode) { | 274 bool TargetMIPS32::doBranchOpt(Inst *Instr, const CfgNode *NextNode) { |
| 275 (void)I; | 275 (void)Instr; |
| 276 (void)NextNode; | 276 (void)NextNode; |
| 277 UnimplementedError(Func->getContext()->getFlags()); | 277 UnimplementedError(Func->getContext()->getFlags()); |
| 278 return false; | 278 return false; |
| 279 } | 279 } |
| 280 | 280 |
| 281 namespace { | 281 namespace { |
| 282 | 282 |
| 283 const char *RegNames[RegMIPS32::Reg_NUM] = { | 283 const char *RegNames[RegMIPS32::Reg_NUM] = { |
| 284 #define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \ | 284 #define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \ |
| 285 isI64Pair, isFP32, isFP64, isVec128, alias_init) \ | 285 isI64Pair, isFP32, isFP64, isVec128, alias_init) \ |
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| 553 if (frameptr && (Exclude & RegSet_FramePointer)) \ | 553 if (frameptr && (Exclude & RegSet_FramePointer)) \ |
| 554 Registers[RegMIPS32::val] = false; | 554 Registers[RegMIPS32::val] = false; |
| 555 | 555 |
| 556 REGMIPS32_TABLE | 556 REGMIPS32_TABLE |
| 557 | 557 |
| 558 #undef X | 558 #undef X |
| 559 | 559 |
| 560 return Registers; | 560 return Registers; |
| 561 } | 561 } |
| 562 | 562 |
| 563 void TargetMIPS32::lowerAlloca(const InstAlloca *Inst) { | 563 void TargetMIPS32::lowerAlloca(const InstAlloca *Instr) { |
| 564 UsesFramePointer = true; | 564 UsesFramePointer = true; |
| 565 // Conservatively require the stack to be aligned. Some stack adjustment | 565 // Conservatively require the stack to be aligned. Some stack adjustment |
| 566 // operations implemented below assume that the stack is aligned before the | 566 // operations implemented below assume that the stack is aligned before the |
| 567 // alloca. All the alloca code ensures that the stack alignment is preserved | 567 // alloca. All the alloca code ensures that the stack alignment is preserved |
| 568 // after the alloca. The stack alignment restriction can be relaxed in some | 568 // after the alloca. The stack alignment restriction can be relaxed in some |
| 569 // cases. | 569 // cases. |
| 570 NeedsStackAlignment = true; | 570 NeedsStackAlignment = true; |
| 571 UnimplementedLoweringError(this, Inst); | 571 UnimplementedLoweringError(this, Instr); |
| 572 } | 572 } |
| 573 | 573 |
| 574 void TargetMIPS32::lowerInt64Arithmetic(const InstArithmetic *Inst, | 574 void TargetMIPS32::lowerInt64Arithmetic(const InstArithmetic *Instr, |
| 575 Variable *Dest, Operand *Src0, | 575 Variable *Dest, Operand *Src0, |
| 576 Operand *Src1) { | 576 Operand *Src1) { |
| 577 InstArithmetic::OpKind Op = Inst->getOp(); | 577 InstArithmetic::OpKind Op = Instr->getOp(); |
| 578 switch (Op) { | 578 switch (Op) { |
| 579 case InstArithmetic::Add: | 579 case InstArithmetic::Add: |
| 580 case InstArithmetic::And: | 580 case InstArithmetic::And: |
| 581 case InstArithmetic::Or: | 581 case InstArithmetic::Or: |
| 582 case InstArithmetic::Sub: | 582 case InstArithmetic::Sub: |
| 583 case InstArithmetic::Xor: | 583 case InstArithmetic::Xor: |
| 584 break; | 584 break; |
| 585 default: | 585 default: |
| 586 UnimplementedLoweringError(this, Inst); | 586 UnimplementedLoweringError(this, Instr); |
| 587 return; | 587 return; |
| 588 } | 588 } |
| 589 auto *DestLo = llvm::cast<Variable>(loOperand(Dest)); | 589 auto *DestLo = llvm::cast<Variable>(loOperand(Dest)); |
| 590 auto *DestHi = llvm::cast<Variable>(hiOperand(Dest)); | 590 auto *DestHi = llvm::cast<Variable>(hiOperand(Dest)); |
| 591 Variable *Src0LoR = legalizeToReg(loOperand(Src0)); | 591 Variable *Src0LoR = legalizeToReg(loOperand(Src0)); |
| 592 Variable *Src1LoR = legalizeToReg(loOperand(Src1)); | 592 Variable *Src1LoR = legalizeToReg(loOperand(Src1)); |
| 593 Variable *Src0HiR = legalizeToReg(hiOperand(Src0)); | 593 Variable *Src0HiR = legalizeToReg(hiOperand(Src0)); |
| 594 Variable *Src1HiR = legalizeToReg(hiOperand(Src1)); | 594 Variable *Src1HiR = legalizeToReg(hiOperand(Src1)); |
| 595 | 595 |
| 596 switch (Op) { | 596 switch (Op) { |
| (...skipping 47 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... | |
| 644 case InstArithmetic::Xor: { | 644 case InstArithmetic::Xor: { |
| 645 Variable *T_Lo = makeReg(IceType_i32); | 645 Variable *T_Lo = makeReg(IceType_i32); |
| 646 Variable *T_Hi = makeReg(IceType_i32); | 646 Variable *T_Hi = makeReg(IceType_i32); |
| 647 _xor(T_Lo, Src0LoR, Src1LoR); | 647 _xor(T_Lo, Src0LoR, Src1LoR); |
| 648 _mov(DestLo, T_Lo); | 648 _mov(DestLo, T_Lo); |
| 649 _xor(T_Hi, Src0HiR, Src1HiR); | 649 _xor(T_Hi, Src0HiR, Src1HiR); |
| 650 _mov(DestHi, T_Hi); | 650 _mov(DestHi, T_Hi); |
| 651 return; | 651 return; |
| 652 } | 652 } |
| 653 default: | 653 default: |
| 654 UnimplementedLoweringError(this, Inst); | 654 UnimplementedLoweringError(this, Instr); |
| 655 return; | 655 return; |
| 656 } | 656 } |
| 657 } | 657 } |
| 658 | 658 |
| 659 void TargetMIPS32::lowerArithmetic(const InstArithmetic *Inst) { | 659 void TargetMIPS32::lowerArithmetic(const InstArithmetic *Instr) { |
| 660 Variable *Dest = Inst->getDest(); | 660 Variable *Dest = Instr->getDest(); |
| 661 // We need to signal all the UnimplementedLoweringError errors before any | 661 // We need to signal all the UnimplementedLoweringError errors before any |
| 662 // legalization into new variables, otherwise Om1 register allocation may fail | 662 // legalization into new variables, otherwise Om1 register allocation may fail |
| 663 // when it sees variables that are defined but not used. | 663 // when it sees variables that are defined but not used. |
| 664 Type DestTy = Dest->getType(); | 664 Type DestTy = Dest->getType(); |
| 665 Operand *Src0 = legalizeUndef(Inst->getSrc(0)); | 665 Operand *Src0 = legalizeUndef(Instr->getSrc(0)); |
| 666 Operand *Src1 = legalizeUndef(Inst->getSrc(1)); | 666 Operand *Src1 = legalizeUndef(Instr->getSrc(1)); |
| 667 if (DestTy == IceType_i64) { | 667 if (DestTy == IceType_i64) { |
| 668 lowerInt64Arithmetic(Inst, Inst->getDest(), Src0, Src1); | 668 lowerInt64Arithmetic(Instr, Instr->getDest(), Src0, Src1); |
| 669 return; | 669 return; |
| 670 } | 670 } |
| 671 if (isVectorType(Dest->getType())) { | 671 if (isVectorType(Dest->getType())) { |
| 672 UnimplementedLoweringError(this, Inst); | 672 UnimplementedLoweringError(this, Instr); |
| 673 return; | 673 return; |
| 674 } | 674 } |
| 675 switch (Inst->getOp()) { | 675 switch (Instr->getOp()) { |
| 676 default: | 676 default: |
| 677 break; | 677 break; |
| 678 case InstArithmetic::Shl: | 678 case InstArithmetic::Shl: |
| 679 case InstArithmetic::Lshr: | 679 case InstArithmetic::Lshr: |
| 680 case InstArithmetic::Ashr: | 680 case InstArithmetic::Ashr: |
| 681 case InstArithmetic::Udiv: | 681 case InstArithmetic::Udiv: |
| 682 case InstArithmetic::Sdiv: | 682 case InstArithmetic::Sdiv: |
| 683 case InstArithmetic::Urem: | 683 case InstArithmetic::Urem: |
| 684 case InstArithmetic::Srem: | 684 case InstArithmetic::Srem: |
| 685 case InstArithmetic::Fadd: | 685 case InstArithmetic::Fadd: |
| 686 case InstArithmetic::Fsub: | 686 case InstArithmetic::Fsub: |
| 687 case InstArithmetic::Fmul: | 687 case InstArithmetic::Fmul: |
| 688 case InstArithmetic::Fdiv: | 688 case InstArithmetic::Fdiv: |
| 689 case InstArithmetic::Frem: | 689 case InstArithmetic::Frem: |
| 690 UnimplementedLoweringError(this, Inst); | 690 UnimplementedLoweringError(this, Instr); |
| 691 return; | 691 return; |
| 692 } | 692 } |
| 693 | 693 |
| 694 // At this point Dest->getType() is non-i64 scalar | 694 // At this point Dest->getType() is non-i64 scalar |
| 695 | 695 |
| 696 Variable *T = makeReg(Dest->getType()); | 696 Variable *T = makeReg(Dest->getType()); |
| 697 Variable *Src0R = legalizeToReg(Src0); | 697 Variable *Src0R = legalizeToReg(Src0); |
| 698 Variable *Src1R = legalizeToReg(Src1); | 698 Variable *Src1R = legalizeToReg(Src1); |
| 699 | 699 |
| 700 switch (Inst->getOp()) { | 700 switch (Instr->getOp()) { |
| 701 case InstArithmetic::_num: | 701 case InstArithmetic::_num: |
| 702 break; | 702 break; |
| 703 case InstArithmetic::Add: | 703 case InstArithmetic::Add: |
| 704 _addu(T, Src0R, Src1R); | 704 _addu(T, Src0R, Src1R); |
| 705 _mov(Dest, T); | 705 _mov(Dest, T); |
| 706 return; | 706 return; |
| 707 case InstArithmetic::And: | 707 case InstArithmetic::And: |
| 708 _and(T, Src0R, Src1R); | 708 _and(T, Src0R, Src1R); |
| 709 _mov(Dest, T); | 709 _mov(Dest, T); |
| 710 return; | 710 return; |
| (...skipping 32 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... | |
| 743 break; | 743 break; |
| 744 case InstArithmetic::Fsub: | 744 case InstArithmetic::Fsub: |
| 745 break; | 745 break; |
| 746 case InstArithmetic::Fmul: | 746 case InstArithmetic::Fmul: |
| 747 break; | 747 break; |
| 748 case InstArithmetic::Fdiv: | 748 case InstArithmetic::Fdiv: |
| 749 break; | 749 break; |
| 750 case InstArithmetic::Frem: | 750 case InstArithmetic::Frem: |
| 751 break; | 751 break; |
| 752 } | 752 } |
| 753 UnimplementedLoweringError(this, Inst); | 753 UnimplementedLoweringError(this, Instr); |
| 754 } | 754 } |
| 755 | 755 |
| 756 void TargetMIPS32::lowerAssign(const InstAssign *Inst) { | 756 void TargetMIPS32::lowerAssign(const InstAssign *Instr) { |
| 757 Variable *Dest = Inst->getDest(); | 757 Variable *Dest = Instr->getDest(); |
| 758 Operand *Src0 = Inst->getSrc(0); | 758 Operand *Src0 = Instr->getSrc(0); |
| 759 assert(Dest->getType() == Src0->getType()); | 759 assert(Dest->getType() == Src0->getType()); |
| 760 if (Dest->getType() == IceType_i64) { | 760 if (Dest->getType() == IceType_i64) { |
| 761 Src0 = legalizeUndef(Src0); | 761 Src0 = legalizeUndef(Src0); |
| 762 Operand *Src0Lo = legalize(loOperand(Src0), Legal_Reg); | 762 Operand *Src0Lo = legalize(loOperand(Src0), Legal_Reg); |
| 763 Operand *Src0Hi = legalize(hiOperand(Src0), Legal_Reg); | 763 Operand *Src0Hi = legalize(hiOperand(Src0), Legal_Reg); |
| 764 auto *DestLo = llvm::cast<Variable>(loOperand(Dest)); | 764 auto *DestLo = llvm::cast<Variable>(loOperand(Dest)); |
| 765 auto *DestHi = llvm::cast<Variable>(hiOperand(Dest)); | 765 auto *DestHi = llvm::cast<Variable>(hiOperand(Dest)); |
| 766 // Variable *T_Lo = nullptr, *T_Hi = nullptr; | 766 // Variable *T_Lo = nullptr, *T_Hi = nullptr; |
| 767 Variable *T_Lo = makeReg(IceType_i32); | 767 Variable *T_Lo = makeReg(IceType_i32); |
| 768 Variable *T_Hi = makeReg(IceType_i32); | 768 Variable *T_Hi = makeReg(IceType_i32); |
| 769 _mov(T_Lo, Src0Lo); | 769 _mov(T_Lo, Src0Lo); |
| 770 _mov(DestLo, T_Lo); | 770 _mov(DestLo, T_Lo); |
| 771 _mov(T_Hi, Src0Hi); | 771 _mov(T_Hi, Src0Hi); |
| 772 _mov(DestHi, T_Hi); | 772 _mov(DestHi, T_Hi); |
| 773 } else { | 773 } else { |
| 774 Operand *SrcR; | 774 Operand *SrcR; |
| 775 if (Dest->hasReg()) { | 775 if (Dest->hasReg()) { |
| 776 // If Dest already has a physical register, then legalize the Src operand | 776 // If Dest already has a physical register, then legalize the Src operand |
| 777 // into a Variable with the same register assignment. This especially | 777 // into a Variable with the same register assignment. This especially |
| 778 // helps allow the use of Flex operands. | 778 // helps allow the use of Flex operands. |
| 779 SrcR = legalize(Src0, Legal_Reg, Dest->getRegNum()); | 779 SrcR = legalize(Src0, Legal_Reg, Dest->getRegNum()); |
| 780 } else { | 780 } else { |
| 781 // Dest could be a stack operand. Since we could potentially need | 781 // Dest could be a stack operand. Since we could potentially need |
| 782 // to do a Store (and store can only have Register operands), | 782 // to do a Store (and store can only have Register operands), |
| 783 // legalize this to a register. | 783 // legalize this to a register. |
| 784 SrcR = legalize(Src0, Legal_Reg); | 784 SrcR = legalize(Src0, Legal_Reg); |
| 785 } | 785 } |
| 786 if (isVectorType(Dest->getType())) { | 786 if (isVectorType(Dest->getType())) { |
| 787 UnimplementedLoweringError(this, Inst); | 787 UnimplementedLoweringError(this, Instr); |
| 788 } else { | 788 } else { |
| 789 _mov(Dest, SrcR); | 789 _mov(Dest, SrcR); |
| 790 } | 790 } |
| 791 } | 791 } |
| 792 } | 792 } |
| 793 | 793 |
| 794 void TargetMIPS32::lowerBr(const InstBr *Inst) { | 794 void TargetMIPS32::lowerBr(const InstBr *Instr) { |
| 795 UnimplementedLoweringError(this, Inst); | 795 UnimplementedLoweringError(this, Instr); |
| 796 } | 796 } |
| 797 | 797 |
| 798 void TargetMIPS32::lowerCall(const InstCall *Instr) { | 798 void TargetMIPS32::lowerCall(const InstCall *Instr) { |
| 799 // TODO(rkotler): assign arguments to registers and stack. Also reserve stack. | 799 // TODO(rkotler): assign arguments to registers and stack. Also reserve stack. |
| 800 if (Instr->getNumArgs()) { | 800 if (Instr->getNumArgs()) { |
| 801 UnimplementedLoweringError(this, Instr); | 801 UnimplementedLoweringError(this, Instr); |
| 802 return; | 802 return; |
| 803 } | 803 } |
| 804 // Generate the call instruction. Assign its result to a temporary with high | 804 // Generate the call instruction. Assign its result to a temporary with high |
| 805 // register allocation weight. | 805 // register allocation weight. |
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| 875 if (isFloatingType(Dest->getType()) || isVectorType(Dest->getType())) { | 875 if (isFloatingType(Dest->getType()) || isVectorType(Dest->getType())) { |
| 876 UnimplementedLoweringError(this, Instr); | 876 UnimplementedLoweringError(this, Instr); |
| 877 return; | 877 return; |
| 878 } else { | 878 } else { |
| 879 _mov(Dest, ReturnReg); | 879 _mov(Dest, ReturnReg); |
| 880 } | 880 } |
| 881 } | 881 } |
| 882 } | 882 } |
| 883 } | 883 } |
| 884 | 884 |
| 885 void TargetMIPS32::lowerCast(const InstCast *Inst) { | 885 void TargetMIPS32::lowerCast(const InstCast *Instr) { |
| 886 InstCast::OpKind CastKind = Inst->getCastKind(); | 886 InstCast::OpKind CastKind = Instr->getCastKind(); |
| 887 switch (CastKind) { | 887 switch (CastKind) { |
| 888 default: | 888 default: |
| 889 Func->setError("Cast type not supported"); | 889 Func->setError("Cast type not supported"); |
| 890 return; | 890 return; |
| 891 case InstCast::Sext: { | 891 case InstCast::Sext: { |
| 892 UnimplementedLoweringError(this, Inst); | 892 UnimplementedLoweringError(this, Instr); |
| 893 break; | 893 break; |
| 894 } | 894 } |
| 895 case InstCast::Zext: { | 895 case InstCast::Zext: { |
| 896 UnimplementedLoweringError(this, Inst); | 896 UnimplementedLoweringError(this, Instr); |
| 897 break; | 897 break; |
| 898 } | 898 } |
| 899 case InstCast::Trunc: { | 899 case InstCast::Trunc: { |
| 900 UnimplementedLoweringError(this, Inst); | 900 UnimplementedLoweringError(this, Instr); |
| 901 break; | 901 break; |
| 902 } | 902 } |
| 903 case InstCast::Fptrunc: | 903 case InstCast::Fptrunc: |
| 904 UnimplementedLoweringError(this, Inst); | 904 UnimplementedLoweringError(this, Instr); |
| 905 break; | 905 break; |
| 906 case InstCast::Fpext: { | 906 case InstCast::Fpext: { |
| 907 UnimplementedLoweringError(this, Inst); | 907 UnimplementedLoweringError(this, Instr); |
| 908 break; | 908 break; |
| 909 } | 909 } |
| 910 case InstCast::Fptosi: | 910 case InstCast::Fptosi: |
| 911 UnimplementedLoweringError(this, Inst); | 911 UnimplementedLoweringError(this, Instr); |
| 912 break; | 912 break; |
| 913 case InstCast::Fptoui: | 913 case InstCast::Fptoui: |
| 914 UnimplementedLoweringError(this, Inst); | 914 UnimplementedLoweringError(this, Instr); |
| 915 break; | 915 break; |
| 916 case InstCast::Sitofp: | 916 case InstCast::Sitofp: |
| 917 UnimplementedLoweringError(this, Inst); | 917 UnimplementedLoweringError(this, Instr); |
| 918 break; | 918 break; |
| 919 case InstCast::Uitofp: { | 919 case InstCast::Uitofp: { |
| 920 UnimplementedLoweringError(this, Inst); | 920 UnimplementedLoweringError(this, Instr); |
| 921 break; | 921 break; |
| 922 } | 922 } |
| 923 case InstCast::Bitcast: { | 923 case InstCast::Bitcast: { |
| 924 UnimplementedLoweringError(this, Inst); | 924 UnimplementedLoweringError(this, Instr); |
| 925 break; | 925 break; |
| 926 } | 926 } |
| 927 } | 927 } |
| 928 } | 928 } |
| 929 | 929 |
| 930 void TargetMIPS32::lowerExtractElement(const InstExtractElement *Inst) { | 930 void TargetMIPS32::lowerExtractElement(const InstExtractElement *Instr) { |
| 931 UnimplementedLoweringError(this, Inst); | 931 UnimplementedLoweringError(this, Instr); |
| 932 } | 932 } |
| 933 | 933 |
| 934 void TargetMIPS32::lowerFcmp(const InstFcmp *Inst) { | 934 void TargetMIPS32::lowerFcmp(const InstFcmp *Instr) { |
| 935 UnimplementedLoweringError(this, Inst); | 935 UnimplementedLoweringError(this, Instr); |
| 936 } | 936 } |
| 937 | 937 |
| 938 void TargetMIPS32::lowerIcmp(const InstIcmp *Inst) { | 938 void TargetMIPS32::lowerIcmp(const InstIcmp *Instr) { |
| 939 UnimplementedLoweringError(this, Inst); | 939 UnimplementedLoweringError(this, Instr); |
| 940 } | 940 } |
| 941 | 941 |
| 942 void TargetMIPS32::lowerInsertElement(const InstInsertElement *Inst) { | 942 void TargetMIPS32::lowerInsertElement(const InstInsertElement *Instr) { |
| 943 UnimplementedLoweringError(this, Inst); | 943 UnimplementedLoweringError(this, Instr); |
| 944 } | 944 } |
| 945 | 945 |
| 946 void TargetMIPS32::lowerIntrinsicCall(const InstIntrinsicCall *Instr) { | 946 void TargetMIPS32::lowerIntrinsicCall(const InstIntrinsicCall *Instr) { |
| 947 switch (Instr->getIntrinsicInfo().ID) { | 947 switch (Instr->getIntrinsicInfo().ID) { |
| 948 case Intrinsics::AtomicCmpxchg: { | 948 case Intrinsics::AtomicCmpxchg: { |
| 949 UnimplementedLoweringError(this, Instr); | 949 UnimplementedLoweringError(this, Instr); |
| 950 return; | 950 return; |
| 951 } | 951 } |
| 952 case Intrinsics::AtomicFence: | 952 case Intrinsics::AtomicFence: |
| 953 UnimplementedLoweringError(this, Instr); | 953 UnimplementedLoweringError(this, Instr); |
| (...skipping 108 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... | |
| 1062 case Intrinsics::Trap: | 1062 case Intrinsics::Trap: |
| 1063 UnimplementedLoweringError(this, Instr); | 1063 UnimplementedLoweringError(this, Instr); |
| 1064 return; | 1064 return; |
| 1065 case Intrinsics::UnknownIntrinsic: | 1065 case Intrinsics::UnknownIntrinsic: |
| 1066 Func->setError("Should not be lowering UnknownIntrinsic"); | 1066 Func->setError("Should not be lowering UnknownIntrinsic"); |
| 1067 return; | 1067 return; |
| 1068 } | 1068 } |
| 1069 return; | 1069 return; |
| 1070 } | 1070 } |
| 1071 | 1071 |
| 1072 void TargetMIPS32::lowerLoad(const InstLoad *Inst) { | 1072 void TargetMIPS32::lowerLoad(const InstLoad *Instr) { |
| 1073 UnimplementedLoweringError(this, Inst); | 1073 UnimplementedLoweringError(this, Instr); |
| 1074 } | 1074 } |
| 1075 | 1075 |
| 1076 void TargetMIPS32::doAddressOptLoad() { | 1076 void TargetMIPS32::doAddressOptLoad() { |
| 1077 UnimplementedError(Func->getContext()->getFlags()); | 1077 UnimplementedError(Func->getContext()->getFlags()); |
| 1078 } | 1078 } |
| 1079 | 1079 |
| 1080 void TargetMIPS32::randomlyInsertNop(float Probability, | 1080 void TargetMIPS32::randomlyInsertNop(float Probability, |
| 1081 RandomNumberGenerator &RNG) { | 1081 RandomNumberGenerator &RNG) { |
| 1082 RandomNumberGeneratorWrapper RNGW(RNG); | 1082 RandomNumberGeneratorWrapper RNGW(RNG); |
| 1083 if (RNGW.getTrueWithProbability(Probability)) { | 1083 if (RNGW.getTrueWithProbability(Probability)) { |
| 1084 UnimplementedError(Func->getContext()->getFlags()); | 1084 UnimplementedError(Func->getContext()->getFlags()); |
| 1085 } | 1085 } |
| 1086 } | 1086 } |
| 1087 | 1087 |
| 1088 void TargetMIPS32::lowerPhi(const InstPhi * /*Inst*/) { | 1088 void TargetMIPS32::lowerPhi(const InstPhi * /*Inst*/) { |
|
Jim Stichnoth
2016/02/03 05:03:23
Maybe change this comment too, for completeness?
rkotlerimgtec
2016/02/03 22:06:38
Done.
| |
| 1089 Func->setError("Phi found in regular instruction list"); | 1089 Func->setError("Phi found in regular instruction list"); |
| 1090 } | 1090 } |
| 1091 | 1091 |
| 1092 void TargetMIPS32::lowerRet(const InstRet *Inst) { | 1092 void TargetMIPS32::lowerRet(const InstRet *Instr) { |
| 1093 Variable *Reg = nullptr; | 1093 Variable *Reg = nullptr; |
| 1094 if (Inst->hasRetValue()) { | 1094 if (Instr->hasRetValue()) { |
| 1095 Operand *Src0 = Inst->getRetValue(); | 1095 Operand *Src0 = Instr->getRetValue(); |
| 1096 switch (Src0->getType()) { | 1096 switch (Src0->getType()) { |
| 1097 case IceType_i1: | 1097 case IceType_i1: |
| 1098 case IceType_i8: | 1098 case IceType_i8: |
| 1099 case IceType_i16: | 1099 case IceType_i16: |
| 1100 case IceType_i32: { | 1100 case IceType_i32: { |
| 1101 // Reg = legalizeToReg(Src0, RegMIPS32::Reg_V0); | 1101 // Reg = legalizeToReg(Src0, RegMIPS32::Reg_V0); |
| 1102 Operand *Src0F = legalize(Src0, Legal_Reg); | 1102 Operand *Src0F = legalize(Src0, Legal_Reg); |
| 1103 Reg = makeReg(Src0F->getType(), RegMIPS32::Reg_V0); | 1103 Reg = makeReg(Src0F->getType(), RegMIPS32::Reg_V0); |
| 1104 _mov(Reg, Src0F); | 1104 _mov(Reg, Src0F); |
| 1105 break; | 1105 break; |
| 1106 } | 1106 } |
| 1107 case IceType_i64: { | 1107 case IceType_i64: { |
| 1108 Src0 = legalizeUndef(Src0); | 1108 Src0 = legalizeUndef(Src0); |
| 1109 Variable *R0 = legalizeToReg(loOperand(Src0), RegMIPS32::Reg_V0); | 1109 Variable *R0 = legalizeToReg(loOperand(Src0), RegMIPS32::Reg_V0); |
| 1110 Variable *R1 = legalizeToReg(hiOperand(Src0), RegMIPS32::Reg_V1); | 1110 Variable *R1 = legalizeToReg(hiOperand(Src0), RegMIPS32::Reg_V1); |
| 1111 Reg = R0; | 1111 Reg = R0; |
| 1112 Context.insert<InstFakeUse>(R1); | 1112 Context.insert<InstFakeUse>(R1); |
| 1113 break; | 1113 break; |
| 1114 } | 1114 } |
| 1115 | 1115 |
| 1116 default: | 1116 default: |
| 1117 UnimplementedLoweringError(this, Inst); | 1117 UnimplementedLoweringError(this, Instr); |
| 1118 } | 1118 } |
| 1119 } | 1119 } |
| 1120 _ret(getPhysicalRegister(RegMIPS32::Reg_RA), Reg); | 1120 _ret(getPhysicalRegister(RegMIPS32::Reg_RA), Reg); |
| 1121 } | 1121 } |
| 1122 | 1122 |
| 1123 void TargetMIPS32::lowerSelect(const InstSelect *Inst) { | 1123 void TargetMIPS32::lowerSelect(const InstSelect *Instr) { |
| 1124 UnimplementedLoweringError(this, Inst); | 1124 UnimplementedLoweringError(this, Instr); |
| 1125 } | 1125 } |
| 1126 | 1126 |
| 1127 void TargetMIPS32::lowerStore(const InstStore *Inst) { | 1127 void TargetMIPS32::lowerStore(const InstStore *Instr) { |
| 1128 UnimplementedLoweringError(this, Inst); | 1128 UnimplementedLoweringError(this, Instr); |
| 1129 } | 1129 } |
| 1130 | 1130 |
| 1131 void TargetMIPS32::doAddressOptStore() { | 1131 void TargetMIPS32::doAddressOptStore() { |
| 1132 UnimplementedError(Func->getContext()->getFlags()); | 1132 UnimplementedError(Func->getContext()->getFlags()); |
| 1133 } | 1133 } |
| 1134 | 1134 |
| 1135 void TargetMIPS32::lowerSwitch(const InstSwitch *Inst) { | 1135 void TargetMIPS32::lowerSwitch(const InstSwitch *Instr) { |
| 1136 UnimplementedLoweringError(this, Inst); | 1136 UnimplementedLoweringError(this, Instr); |
| 1137 } | 1137 } |
| 1138 | 1138 |
| 1139 void TargetMIPS32::lowerUnreachable(const InstUnreachable *Inst) { | 1139 void TargetMIPS32::lowerUnreachable(const InstUnreachable *Instr) { |
| 1140 UnimplementedLoweringError(this, Inst); | 1140 UnimplementedLoweringError(this, Instr); |
| 1141 } | 1141 } |
| 1142 | 1142 |
| 1143 // Turn an i64 Phi instruction into a pair of i32 Phi instructions, to preserve | 1143 // Turn an i64 Phi instruction into a pair of i32 Phi instructions, to preserve |
| 1144 // integrity of liveness analysis. Undef values are also turned into zeroes, | 1144 // integrity of liveness analysis. Undef values are also turned into zeroes, |
| 1145 // since loOperand() and hiOperand() don't expect Undef input. | 1145 // since loOperand() and hiOperand() don't expect Undef input. |
| 1146 void TargetMIPS32::prelowerPhis() { | 1146 void TargetMIPS32::prelowerPhis() { |
| 1147 PhiLowering::prelowerPhis32Bit<TargetMIPS32>(this, Context.getNode(), Func); | 1147 PhiLowering::prelowerPhis32Bit<TargetMIPS32>(this, Context.getNode(), Func); |
| 1148 } | 1148 } |
| 1149 | 1149 |
| 1150 void TargetMIPS32::postLower() { | 1150 void TargetMIPS32::postLower() { |
| (...skipping 148 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... | |
| 1299 Str << "\t.set\t" | 1299 Str << "\t.set\t" |
| 1300 << "nomips16\n"; | 1300 << "nomips16\n"; |
| 1301 } | 1301 } |
| 1302 | 1302 |
| 1303 llvm::SmallBitVector TargetMIPS32::TypeToRegisterSet[RCMIPS32_NUM]; | 1303 llvm::SmallBitVector TargetMIPS32::TypeToRegisterSet[RCMIPS32_NUM]; |
| 1304 llvm::SmallBitVector TargetMIPS32::TypeToRegisterSetUnfiltered[RCMIPS32_NUM]; | 1304 llvm::SmallBitVector TargetMIPS32::TypeToRegisterSetUnfiltered[RCMIPS32_NUM]; |
| 1305 llvm::SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM]; | 1305 llvm::SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM]; |
| 1306 | 1306 |
| 1307 } // end of namespace MIPS32 | 1307 } // end of namespace MIPS32 |
| 1308 } // end of namespace Ice | 1308 } // end of namespace Ice |
| OLD | NEW |