Add VMUL vector instructions to the integrated ARM assembler.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 2739 matching lines @@
   // VMUL (floating-point) - ARM section A8.8.351, encoding A2:
   //   vmul<c>.f64 <Dd>, <Dn>, <Dm>
   //
   // cccc11100D10nnnndddd101sN0M0mmmm where cccc=Cond, s=1, Ddddd=Rd, Nnnnn=Rn,
   // and Mmmmm=Rm.
   constexpr const char *Vmuld = "vmuld";
   constexpr IValueT VmuldOpcode = B21;
   emitVFPddd(Cond, VmuldOpcode, OpDd, OpDn, OpDm, Vmuld);
 }
 
+void AssemblerARM32::vmulqi(Type ElmtTy, const Operand *OpQd,
+                            const Operand *OpQn, const Operand *OpQm) {
+  // VMUL, VMULL (integer and polynomial) - ARM section A8.8.350, encoding A1:
+  //   vmul<c>.<dt> <Qd>, <Qn>, <Qm>
+  //
+  // 111100100Dssnnn0ddd01001NqM1mmm0 where Dddd=Qd, Nnnn=Qn, Mmmm=Qm, and
+  // dt in [i8, i16, i32] where ss is the index.
+  assert(ElmtTy != IceType_i64 && "vmulqi on i64 vector not allowed");
+  constexpr const char *Vmulqi = "vmulqi";
+  constexpr IValueT VmulqiOpcode = B11 | B8 | B4;
+  emitSIMDqqq(VmulqiOpcode, ElmtTy, OpQd, OpQn, OpQm, Vmulqi);
+}
+
+void AssemblerARM32::vmulqf(const Operand *OpQd, const Operand *OpQn,
+                            const Operand *OpQm) {
+  // VMUL (floating-point) - ARM section A8.8.351, encoding A1:
+  //   vmul.f32 <Qd>, <Qn>, <Qm>
+  //
+  // 111100110D00nnn0ddd01101MqM1mmm0 where Dddd=Qd, Nnnn=Qn, and Mmmm=Qm.
+  constexpr const char *Vmulqf = "vmulqf";
+  constexpr IValueT VmulqfOpcode = B24 | B11 | B10 | B8 | B4;
+  emitSIMDqqq(VmulqfOpcode, IceType_f32, OpQd, OpQn, OpQm, Vmulqf);
+}
+
 void AssemblerARM32::vorrq(const Operand *OpQd, const Operand *OpQm,
                            const Operand *OpQn) {
   // VORR (register) - ARM section A8.8.360, encoding A1:
   //   vorr <Qd>, <Qn>, <Qm>
   //
   // 111100100D10nnn0ddd00001N1M1mmm0 where Dddd=OpQd, Nnnn=OpQm, and Mmmm=OpQm.
   constexpr const char *Vorrq = "vorrq";
   constexpr IValueT VorrqOpcode = B21 | B8 | B4;
   constexpr Type ElmtTy = IceType_i8;
   emitSIMDqqq(VorrqOpcode, ElmtTy, OpQd, OpQm, OpQn, Vorrq);
@@ skipping 158 matching lines @@
   constexpr const char *Vsqrts = "vsqrts";
   IValueT Sd = encodeSRegister(OpSd, "Sd", Vsqrts);
   IValueT Sm = encodeSRegister(OpSm, "Sm", Vsqrts);
   constexpr IValueT VsqrtsOpcode = B23 | B21 | B20 | B16 | B7 | B6;
   constexpr IValueT S0 = 0;
   emitVFPsss(Cond, VsqrtsOpcode, Sd, S0, Sm);
 }
 
 } // end of namespace ARM32
 } // end of namespace Ice