Add VMUL vector instructions to the integrated ARM assembler.

src/DartARM32/assembler_arm.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // This is forked from Dart revision df52deea9f25690eb8b66c5995da92b70f7ac1fe
 // Please update the (git) revision if we merge changes from Dart.
 // https://code.google.com/p/dart/wiki/GettingTheSource
 
 #include "vm/globals.h"  // NOLINT
 #if defined(TARGET_ARCH_ARM)
@@ skipping 1260 matching lines @@
 void Assembler::vsubqi(OperandSize sz,
                        QRegister qd, QRegister qn, QRegister qm) {
   EmitSIMDqqq(B24 | B11, sz, qd, qn, qm);
 }
 
 
 void Assembler::vsubqs(QRegister qd, QRegister qn, QRegister qm) {
   EmitSIMDqqq(B21 | B11 | B10 | B8, kSWord, qd, qn, qm);
 }
 
-
+#if 0
+// Moved to ARM32::AssemblerARM32::vmulqi().
 void Assembler::vmulqi(OperandSize sz,
                        QRegister qd, QRegister qn, QRegister qm) {
   EmitSIMDqqq(B11 | B8 | B4, sz, qd, qn, qm);
 }
 
-
+// Moved to ARM32::AssemblerARM32::vmulqf().
 void Assembler::vmulqs(QRegister qd, QRegister qn, QRegister qm) {
   EmitSIMDqqq(B24 | B11 | B10 | B8 | B4, kSWord, qd, qn, qm);
 }
-
+#endif
 
 void Assembler::vshlqi(OperandSize sz,
                        QRegister qd, QRegister qm, QRegister qn) {
   EmitSIMDqqq(B25 | B10, sz, qd, qn, qm);
 }
 
 
 void Assembler::vshlqu(OperandSize sz,
                        QRegister qd, QRegister qm, QRegister qn) {
   EmitSIMDqqq(B25 | B24 | B10, sz, qd, qn, qm);
@@ skipping 2389 matching lines @@
 
 
 const char* Assembler::FpuRegisterName(FpuRegister reg) {
   ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters));
   return fpu_reg_names[reg];
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM