Subzero: Cleanup Inst==>Instr.

src/IceTargetLoweringX86BaseImpl.h

 //===- subzero/src/IceTargetLoweringX86BaseImpl.h - x86 lowering -*- C++ -*-==//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 1361 matching lines @@
 }
 
 template <typename TraitsType>
 llvm::SmallBitVector
 TargetX86Base<TraitsType>::getRegisterSet(RegSetMask Include,
                                           RegSetMask Exclude) const {
   return Traits::getRegisterSet(Ctx->getFlags(), Include, Exclude);
 }
 
 template <typename TraitsType>
-void TargetX86Base<TraitsType>::lowerAlloca(const InstAlloca *Inst) {
+void TargetX86Base<TraitsType>::lowerAlloca(const InstAlloca *Instr) {
   // Conservatively require the stack to be aligned. Some stack adjustment
   // operations implemented below assume that the stack is aligned before the
   // alloca. All the alloca code ensures that the stack alignment is preserved
   // after the alloca. The stack alignment restriction can be relaxed in some
   // cases.
   NeedsStackAlignment = true;
 
   // For default align=0, set it to the real value 1, to avoid any
   // bit-manipulation problems below.
-  const uint32_t AlignmentParam = std::max(1u, Inst->getAlignInBytes());
+  const uint32_t AlignmentParam = std::max(1u, Instr->getAlignInBytes());
 
   // LLVM enforces power of 2 alignment.
   assert(llvm::isPowerOf2_32(AlignmentParam));
   assert(llvm::isPowerOf2_32(Traits::X86_STACK_ALIGNMENT_BYTES));
 
   const uint32_t Alignment =
       std::max(AlignmentParam, Traits::X86_STACK_ALIGNMENT_BYTES);
   const bool OverAligned = Alignment > Traits::X86_STACK_ALIGNMENT_BYTES;
   const bool OptM1 = Ctx->getFlags().getOptLevel() == Opt_m1;
-  const bool AllocaWithKnownOffset = Inst->getKnownFrameOffset();
+  const bool AllocaWithKnownOffset = Instr->getKnownFrameOffset();
   const bool UseFramePointer =
       hasFramePointer() || OverAligned || !AllocaWithKnownOffset || OptM1;
 
   if (UseFramePointer)
     setHasFramePointer();
 
   Variable *esp = getPhysicalRegister(getStackReg(), Traits::WordType);
   if (OverAligned) {
     _and(esp, Ctx->getConstantInt32(-Alignment));
   }
 
-  Variable *Dest = Inst->getDest();
-  Operand *TotalSize = legalize(Inst->getSizeInBytes());
+  Variable *Dest = Instr->getDest();
+  Operand *TotalSize = legalize(Instr->getSizeInBytes());
 
   if (const auto *ConstantTotalSize =
           llvm::dyn_cast<ConstantInteger32>(TotalSize)) {
     const uint32_t Value =
         Utils::applyAlignment(ConstantTotalSize->getValue(), Alignment);
     if (UseFramePointer) {
       _sub_sp(Ctx->getConstantInt32(Value));
     } else {
       // If we don't need a Frame Pointer, this alloca has a known offset to the
       // stack pointer. We don't need adjust the stack pointer, nor assign any
@@ skipping 399 matching lines @@
     // L1:
     //   a.lo = t2
     //   a.hi = t3
     Context.insert(Label);
     _mov(DestLo, T_2);
     _mov(DestHi, T_3);
   }
 }
 
 template <typename TraitsType>
-void TargetX86Base<TraitsType>::lowerArithmetic(const InstArithmetic *Inst) {
-  Variable *Dest = Inst->getDest();
+void TargetX86Base<TraitsType>::lowerArithmetic(const InstArithmetic *Instr) {
+  Variable *Dest = Instr->getDest();
   if (Dest->isRematerializable()) {
     Context.insert<InstFakeDef>(Dest);
     return;
   }
   Type Ty = Dest->getType();
-  Operand *Src0 = legalize(Inst->getSrc(0));
-  Operand *Src1 = legalize(Inst->getSrc(1));
-  if (Inst->isCommutative()) {
+  Operand *Src0 = legalize(Instr->getSrc(0));
+  Operand *Src1 = legalize(Instr->getSrc(1));
+  if (Instr->isCommutative()) {
     uint32_t SwapCount = 0;
     if (!llvm::isa<Variable>(Src0) && llvm::isa<Variable>(Src1)) {
       std::swap(Src0, Src1);
       ++SwapCount;
     }
     if (llvm::isa<Constant>(Src0) && !llvm::isa<Constant>(Src1)) {
       std::swap(Src0, Src1);
       ++SwapCount;
     }
     // Improve two-address code patterns by avoiding a copy to the dest
     // register when one of the source operands ends its lifetime here.
-    if (!Inst->isLastUse(Src0) && Inst->isLastUse(Src1)) {
+    if (!Instr->isLastUse(Src0) && Instr->isLastUse(Src1)) {
       std::swap(Src0, Src1);
       ++SwapCount;
     }
     assert(SwapCount <= 1);
     (void)SwapCount;
   }
   if (!Traits::Is64Bit && Ty == IceType_i64) {
     // These x86-32 helper-call-involved instructions are lowered in this
     // separate switch. This is because loOperand() and hiOperand() may insert
     // redundant instructions for constant blinding and pooling. Such redundant
     // instructions will fail liveness analysis under -Om1 setting. And,
     // actually these arguments do not need to be processed with loOperand()
     // and hiOperand() to be used.
-    switch (Inst->getOp()) {
+    switch (Instr->getOp()) {
     case InstArithmetic::Udiv:
     case InstArithmetic::Sdiv:
     case InstArithmetic::Urem:
     case InstArithmetic::Srem:
       llvm::report_fatal_error("Helper call was expected");
       return;
     default:
       break;
     }
 
     auto *DestLo = llvm::cast<Variable>(loOperand(Dest));
     auto *DestHi = llvm::cast<Variable>(hiOperand(Dest));
     Operand *Src0Lo = loOperand(Src0);
     Operand *Src0Hi = hiOperand(Src0);
     Operand *Src1Lo = loOperand(Src1);
     Operand *Src1Hi = hiOperand(Src1);
     Variable *T_Lo = nullptr, *T_Hi = nullptr;
-    switch (Inst->getOp()) {
+    switch (Instr->getOp()) {
     case InstArithmetic::_num:
       llvm_unreachable("Unknown arithmetic operator");
       break;
     case InstArithmetic::Add:
       _mov(T_Lo, Src0Lo);
       _add(T_Lo, Src1Lo);
       _mov(DestLo, T_Lo);
       _mov(T_Hi, Src0Hi);
       _adc(T_Hi, Src1Hi);
       _mov(DestHi, T_Hi);
@@ skipping 56 matching lines @@
       _mov(DestLo, T_4Lo);
       _add(T_4Hi, T_1);
       _mov(T_2, Src1Hi);
       _imul(T_2, Src0Lo);
       _add(T_4Hi, T_2);
       _mov(DestHi, T_4Hi);
     } break;
     case InstArithmetic::Shl:
     case InstArithmetic::Lshr:
     case InstArithmetic::Ashr:
-      lowerShift64(Inst->getOp(), Src0Lo, Src0Hi, Src1Lo, DestLo, DestHi);
+      lowerShift64(Instr->getOp(), Src0Lo, Src0Hi, Src1Lo, DestLo, DestHi);
       break;
     case InstArithmetic::Fadd:
     case InstArithmetic::Fsub:
     case InstArithmetic::Fmul:
     case InstArithmetic::Fdiv:
     case InstArithmetic::Frem:
       llvm_unreachable("FP instruction with i64 type");
       break;
     case InstArithmetic::Udiv:
     case InstArithmetic::Sdiv:
     case InstArithmetic::Urem:
     case InstArithmetic::Srem:
       llvm_unreachable("Call-helper-involved instruction for i64 type \
                        should have already been handled before");
       break;
     }
     return;
   }
   if (isVectorType(Ty)) {
     // TODO: Trap on integer divide and integer modulo by zero. See:
     // https://code.google.com/p/nativeclient/issues/detail?id=3899
     if (llvm::isa<X86OperandMem>(Src1))
       Src1 = legalizeToReg(Src1);
-    switch (Inst->getOp()) {
+    switch (Instr->getOp()) {
     case InstArithmetic::_num:
       llvm_unreachable("Unknown arithmetic operator");
       break;
     case InstArithmetic::Add: {
       Variable *T = makeReg(Ty);
       _movp(T, Src0);
       _padd(T, Src1);
       _movp(Dest, T);
     } break;
     case InstArithmetic::And: {
@@ skipping 107 matching lines @@
       _movp(Dest, T);
     } break;
     case InstArithmetic::Frem:
       llvm::report_fatal_error("Scalarized operation was expected");
       break;
     }
     return;
   }
   Variable *T_edx = nullptr;
   Variable *T = nullptr;
-  switch (Inst->getOp()) {
+  switch (Instr->getOp()) {
   case InstArithmetic::_num:
     llvm_unreachable("Unknown arithmetic operator");
     break;
   case InstArithmetic::Add:
     _mov(T, Src0);
     _add(T, Src1);
     _mov(Dest, T);
     break;
   case InstArithmetic::And:
     _mov(T, Src0);
@@ skipping 269 matching lines @@
     _divss(T, Src1);
     _mov(Dest, T);
     break;
   case InstArithmetic::Frem:
     llvm::report_fatal_error("Helper call was expected");
     break;
   }
 }
 
 template <typename TraitsType>
-void TargetX86Base<TraitsType>::lowerAssign(const InstAssign *Inst) {
-  Variable *Dest = Inst->getDest();
+void TargetX86Base<TraitsType>::lowerAssign(const InstAssign *Instr) {
+  Variable *Dest = Instr->getDest();
   if (Dest->isRematerializable()) {
     Context.insert<InstFakeDef>(Dest);
     return;
   }
-  Operand *Src = Inst->getSrc(0);
+  Operand *Src = Instr->getSrc(0);
   assert(Dest->getType() == Src->getType());
   lowerMove(Dest, Src, false);
 }
 
 template <typename TraitsType>
 void TargetX86Base<TraitsType>::lowerBr(const InstBr *Br) {
   if (Br->isUnconditional()) {
     _br(Br->getTargetUnconditional());
     return;
   }
@@ skipping 217 matching lines @@
       Variable *DestHi = Dest64On32->getHi();
       _mov(DestLo, ReturnReg);
       _mov(DestHi, ReturnRegHi);
     } else {
       _mov(Dest, ReturnReg);
     }
   }
 }
 
 template <typename TraitsType>
-void TargetX86Base<TraitsType>::lowerCast(const InstCast *Inst) {
+void TargetX86Base<TraitsType>::lowerCast(const InstCast *Instr) {
   // a = cast(b) ==> t=cast(b); a=t; (link t->b, link a->t, no overlap)
-  InstCast::OpKind CastKind = Inst->getCastKind();
-  Variable *Dest = Inst->getDest();
+  InstCast::OpKind CastKind = Instr->getCastKind();
+  Variable *Dest = Instr->getDest();
   Type DestTy = Dest->getType();
   switch (CastKind) {
   default:
     Func->setError("Cast type not supported");
     return;
   case InstCast::Sext: {
     // Src0RM is the source operand legalized to physical register or memory,
     // but not immediate, since the relevant x86 native instructions don't
     // allow an immediate operand. If the operand is an immediate, we could
     // consider computing the strength-reduced result at translation time, but
     // we're unlikely to see something like that in the bitcode that the
     // optimizer wouldn't have already taken care of.
-    Operand *Src0RM = legalize(Inst->getSrc(0), Legal_Reg | Legal_Mem);
+    Operand *Src0RM = legalize(Instr->getSrc(0), Legal_Reg | Legal_Mem);
     if (isVectorType(DestTy)) {
       if (DestTy == IceType_v16i8) {
         // onemask = materialize(1,1,...); dst = (src & onemask) > 0
         Variable *OneMask = makeVectorOfOnes(DestTy);
         Variable *T = makeReg(DestTy);
         _movp(T, Src0RM);
         _pand(T, OneMask);
         Variable *Zeros = makeVectorOfZeros(DestTy);
         _pcmpgt(T, Zeros);
         _movp(Dest, T);
@@ skipping 51 matching lines @@
       _mov(Dest, T);
     } else {
       // t1 = movsx src; dst = t1
       Variable *T = makeReg(DestTy);
       _movsx(T, Src0RM);
       _mov(Dest, T);
     }
     break;
   }
   case InstCast::Zext: {
-    Operand *Src0RM = legalize(Inst->getSrc(0), Legal_Reg | Legal_Mem);
+    Operand *Src0RM = legalize(Instr->getSrc(0), Legal_Reg | Legal_Mem);
     if (isVectorType(DestTy)) {
       // onemask = materialize(1,1,...); dest = onemask & src
       Variable *OneMask = makeVectorOfOnes(DestTy);
       Variable *T = makeReg(DestTy);
       _movp(T, Src0RM);
       _pand(T, OneMask);
       _movp(Dest, T);
     } else if (!Traits::Is64Bit && DestTy == IceType_i64) {
       // t1=movzx src; dst.lo=t1; dst.hi=0
       Constant *Zero = Ctx->getConstantZero(IceType_i32);
@@ skipping 26 matching lines @@
       // t1 = movzx src; dst = t1
       Variable *T = makeReg(DestTy);
       _movzx(T, Src0RM);
       _mov(Dest, T);
     }
     break;
   }
   case InstCast::Trunc: {
     if (isVectorType(DestTy)) {
       // onemask = materialize(1,1,...); dst = src & onemask
-      Operand *Src0RM = legalize(Inst->getSrc(0), Legal_Reg | Legal_Mem);
+      Operand *Src0RM = legalize(Instr->getSrc(0), Legal_Reg | Legal_Mem);
       Type Src0Ty = Src0RM->getType();
       Variable *OneMask = makeVectorOfOnes(Src0Ty);
       Variable *T = makeReg(DestTy);
       _movp(T, Src0RM);
       _pand(T, OneMask);
       _movp(Dest, T);
     } else if (DestTy == IceType_i1 || DestTy == IceType_i8) {
       // Make sure we truncate from and into valid registers.
-      Operand *Src0 = legalizeUndef(Inst->getSrc(0));
+      Operand *Src0 = legalizeUndef(Instr->getSrc(0));
       if (!Traits::Is64Bit && Src0->getType() == IceType_i64)
         Src0 = loOperand(Src0);
       Operand *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
       Variable *T = copyToReg8(Src0RM);
       if (DestTy == IceType_i1)
         _and(T, Ctx->getConstantInt1(1));
       _mov(Dest, T);
     } else {
-      Operand *Src0 = legalizeUndef(Inst->getSrc(0));
+      Operand *Src0 = legalizeUndef(Instr->getSrc(0));
       if (!Traits::Is64Bit && Src0->getType() == IceType_i64)
         Src0 = loOperand(Src0);
       Operand *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
       // t1 = trunc Src0RM; Dest = t1
       Variable *T = makeReg(DestTy);
       _mov(T, Src0RM);
       _mov(Dest, T);
     }
     break;
   }
   case InstCast::Fptrunc:
   case InstCast::Fpext: {
-    Operand *Src0RM = legalize(Inst->getSrc(0), Legal_Reg | Legal_Mem);
+    Operand *Src0RM = legalize(Instr->getSrc(0), Legal_Reg | Legal_Mem);
     // t1 = cvt Src0RM; Dest = t1
     Variable *T = makeReg(DestTy);
     _cvt(T, Src0RM, Traits::Insts::Cvt::Float2float);
     _mov(Dest, T);
     break;
   }
   case InstCast::Fptosi:
     if (isVectorType(DestTy)) {
       assert(DestTy == IceType_v4i32 &&
-             Inst->getSrc(0)->getType() == IceType_v4f32);
-      Operand *Src0RM = legalize(Inst->getSrc(0), Legal_Reg | Legal_Mem);
+             Instr->getSrc(0)->getType() == IceType_v4f32);
+      Operand *Src0RM = legalize(Instr->getSrc(0), Legal_Reg | Legal_Mem);
       if (llvm::isa<X86OperandMem>(Src0RM))
         Src0RM = legalizeToReg(Src0RM);
       Variable *T = makeReg(DestTy);
       _cvt(T, Src0RM, Traits::Insts::Cvt::Tps2dq);
       _movp(Dest, T);
     } else if (!Traits::Is64Bit && DestTy == IceType_i64) {
       llvm::report_fatal_error("Helper call was expected");
     } else {
-      Operand *Src0RM = legalize(Inst->getSrc(0), Legal_Reg | Legal_Mem);
+      Operand *Src0RM = legalize(Instr->getSrc(0), Legal_Reg | Legal_Mem);
       // t1.i32 = cvt Src0RM; t2.dest_type = t1; Dest = t2.dest_type
       Variable *T_1 = nullptr;
       if (Traits::Is64Bit && DestTy == IceType_i64) {
         T_1 = makeReg(IceType_i64);
       } else {
         assert(DestTy != IceType_i64);
         T_1 = makeReg(IceType_i32);
       }
       // cvt() requires its integer argument to be a GPR.
       Variable *T_2 = makeReg(DestTy);
       if (isByteSizedType(DestTy)) {
         assert(T_1->getType() == IceType_i32);
         T_1->setRegClass(RCX86_Is32To8);
         T_2->setRegClass(RCX86_IsTrunc8Rcvr);
       }
       _cvt(T_1, Src0RM, Traits::Insts::Cvt::Tss2si);
       _mov(T_2, T_1); // T_1 and T_2 may have different integer types
       if (DestTy == IceType_i1)
         _and(T_2, Ctx->getConstantInt1(1));
       _mov(Dest, T_2);
     }
     break;
   case InstCast::Fptoui:
     if (isVectorType(DestTy)) {
       llvm::report_fatal_error("Helper call was expected");
     } else if (DestTy == IceType_i64 ||
                (!Traits::Is64Bit && DestTy == IceType_i32)) {
       llvm::report_fatal_error("Helper call was expected");
     } else {
-      Operand *Src0RM = legalize(Inst->getSrc(0), Legal_Reg | Legal_Mem);
+      Operand *Src0RM = legalize(Instr->getSrc(0), Legal_Reg | Legal_Mem);
       // t1.i32 = cvt Src0RM; t2.dest_type = t1; Dest = t2.dest_type
       assert(DestTy != IceType_i64);
       Variable *T_1 = nullptr;
       if (Traits::Is64Bit && DestTy == IceType_i32) {
         T_1 = makeReg(IceType_i64);
       } else {
         assert(DestTy != IceType_i32);
         T_1 = makeReg(IceType_i32);
       }
       Variable *T_2 = makeReg(DestTy);
       if (isByteSizedType(DestTy)) {
         assert(T_1->getType() == IceType_i32);
         T_1->setRegClass(RCX86_Is32To8);
         T_2->setRegClass(RCX86_IsTrunc8Rcvr);
       }
       _cvt(T_1, Src0RM, Traits::Insts::Cvt::Tss2si);
       _mov(T_2, T_1); // T_1 and T_2 may have different integer types
       if (DestTy == IceType_i1)
         _and(T_2, Ctx->getConstantInt1(1));
       _mov(Dest, T_2);
     }
     break;
   case InstCast::Sitofp:
     if (isVectorType(DestTy)) {
       assert(DestTy == IceType_v4f32 &&
-             Inst->getSrc(0)->getType() == IceType_v4i32);
-      Operand *Src0RM = legalize(Inst->getSrc(0), Legal_Reg | Legal_Mem);
+             Instr->getSrc(0)->getType() == IceType_v4i32);
+      Operand *Src0RM = legalize(Instr->getSrc(0), Legal_Reg | Legal_Mem);
       if (llvm::isa<X86OperandMem>(Src0RM))
         Src0RM = legalizeToReg(Src0RM);
       Variable *T = makeReg(DestTy);
       _cvt(T, Src0RM, Traits::Insts::Cvt::Dq2ps);
       _movp(Dest, T);
-    } else if (!Traits::Is64Bit && Inst->getSrc(0)->getType() == IceType_i64) {
+    } else if (!Traits::Is64Bit && Instr->getSrc(0)->getType() == IceType_i64) {
       llvm::report_fatal_error("Helper call was expected");
     } else {
-      Operand *Src0RM = legalize(Inst->getSrc(0), Legal_Reg | Legal_Mem);
+      Operand *Src0RM = legalize(Instr->getSrc(0), Legal_Reg | Legal_Mem);
       // Sign-extend the operand.
       // t1.i32 = movsx Src0RM; t2 = Cvt t1.i32; Dest = t2
       Variable *T_1 = nullptr;
       if (Traits::Is64Bit && Src0RM->getType() == IceType_i64) {
         T_1 = makeReg(IceType_i64);
       } else {
         assert(Src0RM->getType() != IceType_i64);
         T_1 = makeReg(IceType_i32);
       }
       Variable *T_2 = makeReg(DestTy);
       if (Src0RM->getType() == T_1->getType())
         _mov(T_1, Src0RM);
       else
         _movsx(T_1, Src0RM);
       _cvt(T_2, T_1, Traits::Insts::Cvt::Si2ss);
       _mov(Dest, T_2);
     }
     break;
   case InstCast::Uitofp: {
-    Operand *Src0 = Inst->getSrc(0);
+    Operand *Src0 = Instr->getSrc(0);
     if (isVectorType(Src0->getType())) {
       llvm::report_fatal_error("Helper call was expected");
     } else if (Src0->getType() == IceType_i64 ||
                (!Traits::Is64Bit && Src0->getType() == IceType_i32)) {
       llvm::report_fatal_error("Helper call was expected");
     } else {
       Operand *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
       // Zero-extend the operand.
       // t1.i32 = movzx Src0RM; t2 = Cvt t1.i32; Dest = t2
       Variable *T_1 = nullptr;
       if (Traits::Is64Bit && Src0RM->getType() == IceType_i32) {
         T_1 = makeReg(IceType_i64);
       } else {
         assert(Src0RM->getType() != IceType_i64);
         assert(Traits::Is64Bit || Src0RM->getType() != IceType_i32);
         T_1 = makeReg(IceType_i32);
       }
       Variable *T_2 = makeReg(DestTy);
       if (Src0RM->getType() == T_1->getType())
         _mov(T_1, Src0RM);
       else
         _movzx(T_1, Src0RM);
       _cvt(T_2, T_1, Traits::Insts::Cvt::Si2ss);
       _mov(Dest, T_2);
     }
     break;
   }
   case InstCast::Bitcast: {
-    Operand *Src0 = Inst->getSrc(0);
+    Operand *Src0 = Instr->getSrc(0);
     if (DestTy == Src0->getType()) {
       auto *Assign = InstAssign::create(Func, Dest, Src0);
       lowerAssign(Assign);
       return;
     }
     switch (DestTy) {
     default:
       llvm_unreachable("Unexpected Bitcast dest type");
     case IceType_i8: {
       llvm::report_fatal_error("Helper call was expected");
@@ skipping 122 matching lines @@
       _movp(Dest, legalizeToReg(Src0));
     } break;
     }
     break;
   }
   }
 }
 
 template <typename TraitsType>
 void TargetX86Base<TraitsType>::lowerExtractElement(
-    const InstExtractElement *Inst) {
-  Operand *SourceVectNotLegalized = Inst->getSrc(0);
+    const InstExtractElement *Instr) {
+  Operand *SourceVectNotLegalized = Instr->getSrc(0);
   ConstantInteger32 *ElementIndex =
-      llvm::dyn_cast<ConstantInteger32>(Inst->getSrc(1));
+      llvm::dyn_cast<ConstantInteger32>(Instr->getSrc(1));
   // Only constant indices are allowed in PNaCl IR.
   assert(ElementIndex);
 
   unsigned Index = ElementIndex->getValue();
   Type Ty = SourceVectNotLegalized->getType();
   Type ElementTy = typeElementType(Ty);
   Type InVectorElementTy = Traits::getInVectorElementType(Ty);
 
   // TODO(wala): Determine the best lowering sequences for each type.
   bool CanUsePextr = Ty == IceType_v8i16 || Ty == IceType_v8i1 ||
@@ skipping 52 matching lines @@
   if (ElementTy == IceType_i1) {
     // Truncate extracted integers to i1s if necessary.
     Variable *T = makeReg(IceType_i1);
     InstCast *Cast =
         InstCast::create(Func, InstCast::Trunc, T, ExtractedElementR);
     lowerCast(Cast);
     ExtractedElementR = T;
   }
 
   // Copy the element to the destination.
-  Variable *Dest = Inst->getDest();
+  Variable *Dest = Instr->getDest();
   _mov(Dest, ExtractedElementR);
 }
 
 template <typename TraitsType>
 void TargetX86Base<TraitsType>::lowerFcmp(const InstFcmp *Fcmp) {
   Variable *Dest = Fcmp->getDest();
 
   if (isVectorType(Dest->getType())) {
     lowerFcmpVector(Fcmp);
   } else {
@@ skipping 562 matching lines @@
     Context.insert<InstFakeUse>(T);
     Context.insert<InstFakeDef>(Dest);
     _br(Traits::Cond::Br_ne, Br->getTargetTrue(), Br->getTargetFalse());
     return;
   }
   llvm::report_fatal_error("Unexpected consumer type");
 }
 
 template <typename TraitsType>
 void TargetX86Base<TraitsType>::lowerInsertElement(
-    const InstInsertElement *Inst) {
-  Operand *SourceVectNotLegalized = Inst->getSrc(0);
-  Operand *ElementToInsertNotLegalized = Inst->getSrc(1);
+    const InstInsertElement *Instr) {
+  Operand *SourceVectNotLegalized = Instr->getSrc(0);
+  Operand *ElementToInsertNotLegalized = Instr->getSrc(1);
   ConstantInteger32 *ElementIndex =
-      llvm::dyn_cast<ConstantInteger32>(Inst->getSrc(2));
+      llvm::dyn_cast<ConstantInteger32>(Instr->getSrc(2));
   // Only constant indices are allowed in PNaCl IR.
   assert(ElementIndex);
   unsigned Index = ElementIndex->getValue();
   assert(Index < typeNumElements(SourceVectNotLegalized->getType()));
 
   Type Ty = SourceVectNotLegalized->getType();
   Type ElementTy = typeElementType(Ty);
   Type InVectorElementTy = Traits::getInVectorElementType(Ty);
 
   if (ElementTy == IceType_i1) {
@@ skipping 24 matching lines @@
       // the use
       // of r16 and r8 by converting them through getBaseReg(), while emitIAS()
       // validates that the original and base register encodings are the same.
       if (ElementRM->getType() == IceType_i8 &&
           llvm::isa<Variable>(ElementRM)) {
         // Don't use ah/bh/ch/dh for pinsrb.
         ElementRM = copyToReg8(ElementRM);
       }
       _pinsr(T, ElementRM, Ctx->getConstantInt32(Index));
     }
-    _movp(Inst->getDest(), T);
+    _movp(Instr->getDest(), T);
   } else if (Ty == IceType_v4i32 || Ty == IceType_v4f32 || Ty == IceType_v4i1) {
     // Use shufps or movss.
     Variable *ElementR = nullptr;
     Operand *SourceVectRM =
         legalize(SourceVectNotLegalized, Legal_Reg | Legal_Mem);
 
     if (InVectorElementTy == IceType_f32) {
       // ElementR will be in an XMM register since it is floating point.
       ElementR = legalizeToReg(ElementToInsertNotLegalized);
     } else {
       // Copy an integer to an XMM register.
       Operand *T = legalize(ElementToInsertNotLegalized, Legal_Reg | Legal_Mem);
       ElementR = makeReg(Ty);
       _movd(ElementR, T);
     }
 
     if (Index == 0) {
       Variable *T = makeReg(Ty);
       _movp(T, SourceVectRM);
       _movss(T, ElementR);
-      _movp(Inst->getDest(), T);
+      _movp(Instr->getDest(), T);
       return;
     }
 
     // shufps treats the source and destination operands as vectors of four
     // doublewords. The destination's two high doublewords are selected from
     // the source operand and the two low doublewords are selected from the
     // (original value of) the destination operand. An insertelement operation
     // can be effected with a sequence of two shufps operations with
     // appropriate masks. In all cases below, Element[0] is being inserted into
     // SourceVectOperand. Indices are ordered from left to right.
@@ skipping 13 matching lines @@
     //   T := T[0, 1] ElementR[3, 0]
     const unsigned char Mask1[3] = {0, 192, 128};
     const unsigned char Mask2[3] = {227, 196, 52};
 
     Constant *Mask1Constant = Ctx->getConstantInt32(Mask1[Index - 1]);
     Constant *Mask2Constant = Ctx->getConstantInt32(Mask2[Index - 1]);
 
     if (Index == 1) {
       _shufps(ElementR, SourceVectRM, Mask1Constant);
       _shufps(ElementR, SourceVectRM, Mask2Constant);
-      _movp(Inst->getDest(), ElementR);
+      _movp(Instr->getDest(), ElementR);
     } else {
       Variable *T = makeReg(Ty);
       _movp(T, SourceVectRM);
       _shufps(ElementR, T, Mask1Constant);
       _shufps(T, ElementR, Mask2Constant);
-      _movp(Inst->getDest(), T);
+      _movp(Instr->getDest(), T);
     }
   } else {
     assert(Ty == IceType_v16i8 || Ty == IceType_v16i1);
     // Spill the value to a stack slot and perform the insertion in memory.
     //
     // TODO(wala): use legalize(SourceVectNotLegalized, Legal_Mem) when support
     // for legalizing to mem is implemented.
     Variable *Slot = Func->makeVariable(Ty);
     Slot->setMustNotHaveReg();
     _movp(Slot, legalizeToReg(SourceVectNotLegalized));
 
     // Compute the location of the position to insert in memory.
     unsigned Offset = Index * typeWidthInBytes(InVectorElementTy);
     X86OperandMem *Loc =
         getMemoryOperandForStackSlot(InVectorElementTy, Slot, Offset);
     _store(legalizeToReg(ElementToInsertNotLegalized), Loc);
 
     Variable *T = makeReg(Ty);
     _movp(T, Slot);
-    _movp(Inst->getDest(), T);
+    _movp(Instr->getDest(), T);
   }
 }
 
 template <typename TraitsType>
 void TargetX86Base<TraitsType>::lowerIntrinsicCall(
     const InstIntrinsicCall *Instr) {
   switch (Intrinsics::IntrinsicID ID = Instr->getIntrinsicInfo().ID) {
   case Intrinsics::AtomicCmpxchg: {
     if (!Intrinsics::isMemoryOrderValid(
             ID, getConstantMemoryOrder(Instr->getArg(3)),
@@ skipping 1097 matching lines @@
   inline const Inst *matchShiftedIndex(Variable **Index, uint16_t *Shift);
 
   inline const Inst *matchOffsetBase(Variable **Base,
                                      ConstantRelocatable **Relocatable,
                                      int32_t *Offset);
 
 private:
   const Cfg *const Func;
   const VariablesMetadata *const VMetadata;
 
-  static bool isAdd(const Inst *Inst) {
-    if (auto *Arith = llvm::dyn_cast_or_null<const InstArithmetic>(Inst)) {
+  static bool isAdd(const Inst *Instr) {
+    if (auto *Arith = llvm::dyn_cast_or_null<const InstArithmetic>(Instr)) {
       return (Arith->getOp() == InstArithmetic::Add);
     }
     return false;
   }
 };
 
 void AddressOptimizer::dumpAddressOpt(
     const ConstantRelocatable *const Relocatable, int32_t Offset,
     const Variable *Base, const Variable *Index, uint16_t Shift,
     const Inst *Reason) const {
@@ skipping 492 matching lines @@
   Variable *DestLoad = Load->getDest();
   Type Ty = DestLoad->getType();
   Operand *Src0 = formMemoryOperand(Load->getSourceAddress(), Ty);
   doMockBoundsCheck(Src0);
   auto *Assign = InstAssign::create(Func, DestLoad, Src0);
   lowerAssign(Assign);
 }
 
 template <typename TraitsType>
 void TargetX86Base<TraitsType>::doAddressOptLoad() {
-  Inst *Inst = Context.getCur();
-  Operand *Addr = Inst->getSrc(0);
-  Variable *Dest = Inst->getDest();
-  if (auto *OptAddr = computeAddressOpt(Inst, Dest->getType(), Addr)) {
-    Inst->setDeleted();
+  Inst *Instr = Context.getCur();
+  Operand *Addr = Instr->getSrc(0);
+  Variable *Dest = Instr->getDest();
+  if (auto *OptAddr = computeAddressOpt(Instr, Dest->getType(), Addr)) {
+    Instr->setDeleted();
     Context.insert<InstLoad>(Dest, OptAddr);
   }
 }
 
 template <typename TraitsType>
 void TargetX86Base<TraitsType>::randomlyInsertNop(float Probability,
                                                   RandomNumberGenerator &RNG) {
   RandomNumberGeneratorWrapper RNGW(RNG);
   if (RNGW.getTrueWithProbability(Probability)) {
     _nop(RNGW(Traits::X86_NUM_NOP_VARIANTS));
   }
 }
 
 template <typename TraitsType>
-void TargetX86Base<TraitsType>::lowerPhi(const InstPhi * /*Inst*/) {
+void TargetX86Base<TraitsType>::lowerPhi(const InstPhi * /*Instr*/) {
   Func->setError("Phi found in regular instruction list");
 }
 
 template <typename TraitsType>
-void TargetX86Base<TraitsType>::lowerRet(const InstRet *Inst) {
+void TargetX86Base<TraitsType>::lowerRet(const InstRet *Instr) {
   Variable *Reg = nullptr;
-  if (Inst->hasRetValue()) {
-    Operand *RetValue = legalize(Inst->getRetValue());
+  if (Instr->hasRetValue()) {
+    Operand *RetValue = legalize(Instr->getRetValue());
     const Type ReturnType = RetValue->getType();
     assert(isVectorType(ReturnType) || isScalarFloatingType(ReturnType) ||
            (ReturnType == IceType_i32) || (ReturnType == IceType_i64));
     Reg = moveReturnValueToRegister(RetValue, ReturnType);
   }
   // Add a ret instruction even if sandboxing is enabled, because addEpilog
   // explicitly looks for a ret instruction as a marker for where to insert the
   // frame removal instructions.
   _ret(Reg);
   // Add a fake use of esp to make sure esp stays alive for the entire
@@ skipping 162 matching lines @@
   Variable *Dest = Icmp->getDest();
   if (isVectorType(Dest->getType())) {
     lowerIcmpVector(Icmp);
   } else {
     constexpr Inst *Consumer = nullptr;
     lowerIcmpAndConsumer(Icmp, Consumer);
   }
 }
 
 template <typename TraitsType>
-void TargetX86Base<TraitsType>::lowerSelectVector(const InstSelect *Inst) {
-  Variable *Dest = Inst->getDest();
+void TargetX86Base<TraitsType>::lowerSelectVector(const InstSelect *Instr) {
+  Variable *Dest = Instr->getDest();
   Type DestTy = Dest->getType();
-  Operand *SrcT = Inst->getTrueOperand();
-  Operand *SrcF = Inst->getFalseOperand();
-  Operand *Condition = Inst->getCondition();
+  Operand *SrcT = Instr->getTrueOperand();
+  Operand *SrcF = Instr->getFalseOperand();
+  Operand *Condition = Instr->getCondition();
 
   if (!isVectorType(DestTy))
     llvm::report_fatal_error("Expected a vector select");
 
   Type SrcTy = SrcT->getType();
   Variable *T = makeReg(SrcTy);
   Operand *SrcTRM = legalize(SrcT, Legal_Reg | Legal_Mem);
   Operand *SrcFRM = legalize(SrcF, Legal_Reg | Legal_Mem);
   if (InstructionSet >= Traits::SSE4_1) {
     // TODO(wala): If the condition operand is a constant, use blendps or
@@ skipping 42 matching lines @@
   _movp(T2, T);
   _pand(T, SrcTRM);
   _pandn(T2, SrcFRM);
   _por(T, T2);
   _movp(Dest, T);
 
   return;
 }
 
 template <typename TraitsType>
-void TargetX86Base<TraitsType>::lowerStore(const InstStore *Inst) {
-  Operand *Value = Inst->getData();
-  Operand *Addr = Inst->getAddr();
+void TargetX86Base<TraitsType>::lowerStore(const InstStore *Instr) {
+  Operand *Value = Instr->getData();
+  Operand *Addr = Instr->getAddr();
   X86OperandMem *NewAddr = formMemoryOperand(Addr, Value->getType());
   doMockBoundsCheck(NewAddr);
   Type Ty = NewAddr->getType();
 
   if (!Traits::Is64Bit && Ty == IceType_i64) {
     Value = legalizeUndef(Value);
     Operand *ValueHi = legalize(hiOperand(Value), Legal_Reg | Legal_Imm);
     _store(ValueHi, llvm::cast<X86OperandMem>(hiOperand(NewAddr)));
     Operand *ValueLo = legalize(loOperand(Value), Legal_Reg | Legal_Imm);
     _store(ValueLo, llvm::cast<X86OperandMem>(loOperand(NewAddr)));
   } else if (isVectorType(Ty)) {
     _storep(legalizeToReg(Value), NewAddr);
   } else {
     Value = legalize(Value, Legal_Reg | Legal_Imm);
     _store(Value, NewAddr);
   }
 }
 
 template <typename TraitsType>
 void TargetX86Base<TraitsType>::doAddressOptStore() {
-  auto *Inst = llvm::cast<InstStore>(Context.getCur());
-  Operand *Addr = Inst->getAddr();
-  Operand *Data = Inst->getData();
-  if (auto *OptAddr = computeAddressOpt(Inst, Data->getType(), Addr)) {
-    Inst->setDeleted();
+  auto *Instr = llvm::cast<InstStore>(Context.getCur());
+  Operand *Addr = Instr->getAddr();
+  Operand *Data = Instr->getData();
+  if (auto *OptAddr = computeAddressOpt(Instr, Data->getType(), Addr)) {
+    Instr->setDeleted();
     auto *NewStore = Context.insert<InstStore>(Data, OptAddr);
-    if (Inst->getDest())
-      NewStore->setRmwBeacon(Inst->getRmwBeacon());
+    if (Instr->getDest())
+      NewStore->setRmwBeacon(Instr->getRmwBeacon());
   }
 }
 
 template <typename TraitsType>
 Operand *TargetX86Base<TraitsType>::lowerCmpRange(Operand *Comparison,
                                                   uint64_t Min, uint64_t Max) {
   // TODO(ascull): 64-bit should not reach here but only because it is not
   // implemented yet. This should be able to handle the 64-bit case.
   assert(Traits::Is64Bit || Comparison->getType() != IceType_i64);
   // Subtracting 0 is a nop so don't do it
@@ skipping 86 matching lines @@
       _br(Traits::Cond::Br_be, Case.getTarget());
     }
     if (DefaultTarget != nullptr)
       _br(DefaultTarget);
     return;
   }
   }
 }
 
 template <typename TraitsType>
-void TargetX86Base<TraitsType>::lowerSwitch(const InstSwitch *Inst) {
+void TargetX86Base<TraitsType>::lowerSwitch(const InstSwitch *Instr) {
   // Group cases together and navigate through them with a binary search
-  CaseClusterArray CaseClusters = CaseCluster::clusterizeSwitch(Func, Inst);
-  Operand *Src0 = Inst->getComparison();
-  CfgNode *DefaultTarget = Inst->getLabelDefault();
+  CaseClusterArray CaseClusters = CaseCluster::clusterizeSwitch(Func, Instr);
+  Operand *Src0 = Instr->getComparison();
+  CfgNode *DefaultTarget = Instr->getLabelDefault();
 
   assert(CaseClusters.size() != 0); // Should always be at least one
 
   if (!Traits::Is64Bit && Src0->getType() == IceType_i64) {
     Src0 = legalize(Src0); // get Base/Index into physical registers
     Operand *Src0Lo = loOperand(Src0);
     Operand *Src0Hi = hiOperand(Src0);
     if (CaseClusters.back().getHigh() > UINT32_MAX) {
       // TODO(ascull): handle 64-bit case properly (currently naive version)
       // This might be handled by a higher level lowering of switches.
-      SizeT NumCases = Inst->getNumCases();
+      SizeT NumCases = Instr->getNumCases();
       if (NumCases >= 2) {
         Src0Lo = legalizeToReg(Src0Lo);
         Src0Hi = legalizeToReg(Src0Hi);
       } else {
         Src0Lo = legalize(Src0Lo, Legal_Reg | Legal_Mem);
         Src0Hi = legalize(Src0Hi, Legal_Reg | Legal_Mem);
       }
       for (SizeT I = 0; I < NumCases; ++I) {
-        Constant *ValueLo = Ctx->getConstantInt32(Inst->getValue(I));
-        Constant *ValueHi = Ctx->getConstantInt32(Inst->getValue(I) >> 32);
+        Constant *ValueLo = Ctx->getConstantInt32(Instr->getValue(I));
+        Constant *ValueHi = Ctx->getConstantInt32(Instr->getValue(I) >> 32);
         InstX86Label *Label = InstX86Label::create(Func, this);
         _cmp(Src0Lo, ValueLo);
         _br(Traits::Cond::Br_ne, Label);
         _cmp(Src0Hi, ValueHi);
-        _br(Traits::Cond::Br_e, Inst->getLabel(I));
+        _br(Traits::Cond::Br_e, Instr->getLabel(I));
         Context.insert(Label);
       }
-      _br(Inst->getLabelDefault());
+      _br(Instr->getLabelDefault());
       return;
     } else {
       // All the values are 32-bit so just check the operand is too and then
       // fall through to the 32-bit implementation. This is a common case.
       Src0Hi = legalize(Src0Hi, Legal_Reg | Legal_Mem);
       Constant *Zero = Ctx->getConstantInt32(0);
       _cmp(Src0Hi, Zero);
       _br(Traits::Cond::Br_ne, DefaultTarget);
       Src0 = Src0Lo;
     }
@@ skipping 141 matching lines @@
       NextCast->setDeleted();
       _movp(NextCast->getDest(), legalizeToReg(SignExtendedResult));
       // Skip over the instruction.
       Context.advanceNext();
     }
   }
 }
 
 template <typename TraitsType>
 void TargetX86Base<TraitsType>::lowerUnreachable(
-    const InstUnreachable * /*Inst*/) {
+    const InstUnreachable * /*Instr*/) {
   _ud2();
   // Add a fake use of esp to make sure esp adjustments after the unreachable
   // do not get dead-code eliminated.
   keepEspLiveAtExit();
 }
 
 template <typename TraitsType>
 void TargetX86Base<TraitsType>::lowerRMW(const InstX86FakeRMW *RMW) {
   // If the beacon variable's live range does not end in this instruction, then
   // it must end in the modified Store instruction that follows. This means
@@ skipping 1318 matching lines @@
         emitGlobal(*Var, SectionSuffix);
       }
     }
   } break;
   }
 }
 } // end of namespace X86NAMESPACE
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASEIMPL_H