Subzero: Cleanup Inst==>Instr.

src/IceTargetLoweringARM32.cpp

 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 1906 matching lines @@
       Registers[i] = false;
     if (Entry.StackPtr && (Exclude & RegSet_StackPointer))
       Registers[i] = false;
     if (Entry.FramePtr && (Exclude & RegSet_FramePointer))
       Registers[i] = false;
   }
 
   return Registers;
 }
 
-void TargetARM32::lowerAlloca(const InstAlloca *Inst) {
+void TargetARM32::lowerAlloca(const InstAlloca *Instr) {
   // Conservatively require the stack to be aligned. Some stack adjustment
   // operations implemented below assume that the stack is aligned before the
   // alloca. All the alloca code ensures that the stack alignment is preserved
   // after the alloca. The stack alignment restriction can be relaxed in some
   // cases.
   NeedsStackAlignment = true;
 
   // For default align=0, set it to the real value 1, to avoid any
   // bit-manipulation problems below.
-  const uint32_t AlignmentParam = std::max(1u, Inst->getAlignInBytes());
+  const uint32_t AlignmentParam = std::max(1u, Instr->getAlignInBytes());
 
   // LLVM enforces power of 2 alignment.
   assert(llvm::isPowerOf2_32(AlignmentParam));
   assert(llvm::isPowerOf2_32(ARM32_STACK_ALIGNMENT_BYTES));
 
   const uint32_t Alignment =
       std::max(AlignmentParam, ARM32_STACK_ALIGNMENT_BYTES);
   const bool OverAligned = Alignment > ARM32_STACK_ALIGNMENT_BYTES;
   const bool OptM1 = Ctx->getFlags().getOptLevel() == Opt_m1;
-  const bool AllocaWithKnownOffset = Inst->getKnownFrameOffset();
+  const bool AllocaWithKnownOffset = Instr->getKnownFrameOffset();
   const bool UseFramePointer =
       hasFramePointer() || OverAligned || !AllocaWithKnownOffset || OptM1;
 
   if (UseFramePointer)
     setHasFramePointer();
 
   Variable *SP = getPhysicalRegister(RegARM32::Reg_sp);
   if (OverAligned) {
     Sandboxer(this).align_sp(Alignment);
   }
 
-  Variable *Dest = Inst->getDest();
-  Operand *TotalSize = Inst->getSizeInBytes();
+  Variable *Dest = Instr->getDest();
+  Operand *TotalSize = Instr->getSizeInBytes();
 
   if (const auto *ConstantTotalSize =
           llvm::dyn_cast<ConstantInteger32>(TotalSize)) {
     const uint32_t Value =
         Utils::applyAlignment(ConstantTotalSize->getValue(), Alignment);
     // Constant size alloca.
     if (!UseFramePointer) {
       // If we don't need a Frame Pointer, this alloca has a known offset to the
       // stack pointer. We don't need adjust the stack pointer, nor assign any
       // value to Dest, as Dest is rematerializable.
@@ skipping 84 matching lines @@
       _mls(T2, T, T1R, T0R);
       T = T2;
     }
     _mov(Dest, T);
   } else {
     llvm::report_fatal_error("div should have already been turned into a call");
   }
 }
 
 TargetARM32::SafeBoolChain
-TargetARM32::lowerInt1Arithmetic(const InstArithmetic *Inst) {
-  Variable *Dest = Inst->getDest();
+TargetARM32::lowerInt1Arithmetic(const InstArithmetic *Instr) {
+  Variable *Dest = Instr->getDest();
   assert(Dest->getType() == IceType_i1);
 
-  // So folding didn't work for Inst. Not a problem: We just need to
+  // So folding didn't work for Instr. Not a problem: We just need to
   // materialize the Sources, and perform the operation. We create regular
   // Variables (and not infinite-weight ones) because this call might recurse a
   // lot, and we might end up with tons of infinite weight temporaries.
-  assert(Inst->getSrcSize() == 2);
+  assert(Instr->getSrcSize() == 2);
   Variable *Src0 = Func->makeVariable(IceType_i1);
-  SafeBoolChain Src0Safe = lowerInt1(Src0, Inst->getSrc(0));
+  SafeBoolChain Src0Safe = lowerInt1(Src0, Instr->getSrc(0));
 
-  Operand *Src1 = Inst->getSrc(1);
+  Operand *Src1 = Instr->getSrc(1);
   SafeBoolChain Src1Safe = SBC_Yes;
 
   if (!llvm::isa<Constant>(Src1)) {
     Variable *Src1V = Func->makeVariable(IceType_i1);
     Src1Safe = lowerInt1(Src1V, Src1);
     Src1 = Src1V;
   }
 
   Variable *T = makeReg(IceType_i1);
   Src0 = legalizeToReg(Src0);
   Operand *Src1RF = legalize(Src1, Legal_Reg | Legal_Flex);
-  switch (Inst->getOp()) {
+  switch (Instr->getOp()) {
   default:
     // If this Unreachable is ever executed, add the offending operation to
     // the list of valid consumers.
     llvm::report_fatal_error("Unhandled i1 Op");
   case InstArithmetic::And:
     _and(T, Src0, Src1RF);
     break;
   case InstArithmetic::Or:
     _orr(T, Src0, Src1RF);
     break;
@@ skipping 1068 matching lines @@
   case InstArithmetic::Fsub:
   case InstArithmetic::Fmul:
   case InstArithmetic::Fdiv:
   case InstArithmetic::Frem:
     llvm::report_fatal_error(
         "Floating point arith should have been handled earlier.");
     return;
   }
 }
 
-void TargetARM32::lowerAssign(const InstAssign *Inst) {
-  Variable *Dest = Inst->getDest();
+void TargetARM32::lowerAssign(const InstAssign *Instr) {
+  Variable *Dest = Instr->getDest();
 
   if (Dest->isRematerializable()) {
     Context.insert<InstFakeDef>(Dest);
     return;
   }
 
-  Operand *Src0 = Inst->getSrc(0);
+  Operand *Src0 = Instr->getSrc(0);
   assert(Dest->getType() == Src0->getType());
   if (Dest->getType() == IceType_i64) {
     Src0 = legalizeUndef(Src0);
 
     Variable *T_Lo = makeReg(IceType_i32);
     auto *DestLo = llvm::cast<Variable>(loOperand(Dest));
     Operand *Src0Lo = legalize(loOperand(Src0), Legal_Reg | Legal_Flex);
     _mov(T_Lo, Src0Lo);
     _mov(DestLo, T_Lo);
 
@@ skipping 340 matching lines @@
 }
 
 namespace {
 void configureBitcastTemporary(Variable64On32 *Var) {
   Var->setMustNotHaveReg();
   Var->getHi()->setMustHaveReg();
   Var->getLo()->setMustHaveReg();
 }
 } // end of anonymous namespace
 
-void TargetARM32::lowerCast(const InstCast *Inst) {
-  InstCast::OpKind CastKind = Inst->getCastKind();
-  Variable *Dest = Inst->getDest();
-  Operand *Src0 = legalizeUndef(Inst->getSrc(0));
+void TargetARM32::lowerCast(const InstCast *Instr) {
+  InstCast::OpKind CastKind = Instr->getCastKind();
+  Variable *Dest = Instr->getDest();
+  Operand *Src0 = legalizeUndef(Instr->getSrc(0));
   switch (CastKind) {
   default:
     Func->setError("Cast type not supported");
     return;
   case InstCast::Sext: {
     if (isVectorType(Dest->getType())) {
-      UnimplementedLoweringError(this, Inst);
+      UnimplementedLoweringError(this, Instr);
     } else if (Dest->getType() == IceType_i64) {
       // t1=sxtb src; t2= mov t1 asr #31; dst.lo=t1; dst.hi=t2
       Constant *ShiftAmt = Ctx->getConstantInt32(31);
       auto *DestLo = llvm::cast<Variable>(loOperand(Dest));
       auto *DestHi = llvm::cast<Variable>(hiOperand(Dest));
       Variable *T_Lo = makeReg(DestLo->getType());
       if (Src0->getType() == IceType_i32) {
         Operand *Src0RF = legalize(Src0, Legal_Reg | Legal_Flex);
         _mov(T_Lo, Src0RF);
       } else if (Src0->getType() != IceType_i1) {
@@ skipping 24 matching lines @@
       Constant *_0 = Ctx->getConstantZero(IceType_i32);
       Operand *_m1 = Ctx->getConstantInt(Dest->getType(), -1);
       Variable *T = makeReg(Dest->getType());
       lowerInt1ForSelect(T, Src0, _m1, _0);
       _mov(Dest, T);
     }
     break;
   }
   case InstCast::Zext: {
     if (isVectorType(Dest->getType())) {
-      UnimplementedLoweringError(this, Inst);
+      UnimplementedLoweringError(this, Instr);
     } else if (Dest->getType() == IceType_i64) {
       // t1=uxtb src; dst.lo=t1; dst.hi=0
       Operand *_0 =
           legalize(Ctx->getConstantZero(IceType_i32), Legal_Reg | Legal_Flex);
       auto *DestLo = llvm::cast<Variable>(loOperand(Dest));
       auto *DestHi = llvm::cast<Variable>(hiOperand(Dest));
       Variable *T_Lo = makeReg(DestLo->getType());
 
       switch (Src0->getType()) {
       default: {
@@ skipping 32 matching lines @@
       // t1 = uxt src; dst = t1
       Variable *Src0R = legalizeToReg(Src0);
       Variable *T = makeReg(Dest->getType());
       _uxt(T, Src0R);
       _mov(Dest, T);
     }
     break;
   }
   case InstCast::Trunc: {
     if (isVectorType(Dest->getType())) {
-      UnimplementedLoweringError(this, Inst);
+      UnimplementedLoweringError(this, Instr);
     } else {
       if (Src0->getType() == IceType_i64)
         Src0 = loOperand(Src0);
       Operand *Src0RF = legalize(Src0, Legal_Reg | Legal_Flex);
       // t1 = trunc Src0RF; Dest = t1
       Variable *T = makeReg(Dest->getType());
       _mov(T, Src0RF);
       if (Dest->getType() == IceType_i1)
         _and(T, T, Ctx->getConstantInt1(1));
       _mov(Dest, T);
     }
     break;
   }
   case InstCast::Fptrunc:
   case InstCast::Fpext: {
     // fptrunc: dest.f32 = fptrunc src0.fp64
     // fpext: dest.f64 = fptrunc src0.fp32
     const bool IsTrunc = CastKind == InstCast::Fptrunc;
     if (isVectorType(Dest->getType())) {
-      UnimplementedLoweringError(this, Inst);
+      UnimplementedLoweringError(this, Instr);
       break;
     }
     assert(Dest->getType() == (IsTrunc ? IceType_f32 : IceType_f64));
     assert(Src0->getType() == (IsTrunc ? IceType_f64 : IceType_f32));
     Variable *Src0R = legalizeToReg(Src0);
     Variable *T = makeReg(Dest->getType());
     _vcvt(T, Src0R, IsTrunc ? InstARM32Vcvt::D2s : InstARM32Vcvt::S2d);
     _mov(Dest, T);
     break;
   }
   case InstCast::Fptosi:
   case InstCast::Fptoui: {
     if (isVectorType(Dest->getType())) {
-      UnimplementedLoweringError(this, Inst);
+      UnimplementedLoweringError(this, Instr);
       break;
     }
 
     const bool DestIsSigned = CastKind == InstCast::Fptosi;
     const bool Src0IsF32 = isFloat32Asserting32Or64(Src0->getType());
     if (llvm::isa<Variable64On32>(Dest)) {
       llvm::report_fatal_error("fp-to-i64 should have been pre-lowered.");
     }
     // fptosi:
     //     t1.fp = vcvt src0.fp
@@ skipping 15 matching lines @@
       Variable *T_1 = makeReg(Dest->getType());
       lowerCast(InstCast::create(Func, InstCast::Trunc, T_1, T));
       T = T_1;
     }
     _mov(Dest, T);
     break;
   }
   case InstCast::Sitofp:
   case InstCast::Uitofp: {
     if (isVectorType(Dest->getType())) {
-      UnimplementedLoweringError(this, Inst);
+      UnimplementedLoweringError(this, Instr);
       break;
     }
     const bool SourceIsSigned = CastKind == InstCast::Sitofp;
     const bool DestIsF32 = isFloat32Asserting32Or64(Dest->getType());
     if (Src0->getType() == IceType_i64) {
       llvm::report_fatal_error("i64-to-fp should have been pre-lowered.");
     }
     // sitofp:
     //     t1.i32 = sext src.int    @ sign-extends src0 if needed.
     //     t2.fp32 = vmov t1.i32
@@ skipping 16 matching lines @@
     Variable *T = makeReg(Dest->getType());
     const InstARM32Vcvt::VcvtVariant Conversion =
         DestIsF32
             ? (SourceIsSigned ? InstARM32Vcvt::Si2s : InstARM32Vcvt::Ui2s)
             : (SourceIsSigned ? InstARM32Vcvt::Si2d : InstARM32Vcvt::Ui2d);
     _vcvt(T, Src0R, Conversion);
     _mov(Dest, T);
     break;
   }
   case InstCast::Bitcast: {
-    Operand *Src0 = Inst->getSrc(0);
+    Operand *Src0 = Instr->getSrc(0);
     if (Dest->getType() == Src0->getType()) {
       auto *Assign = InstAssign::create(Func, Dest, Src0);
       lowerAssign(Assign);
       return;
     }
     Type DestType = Dest->getType();
     switch (DestType) {
     case IceType_NUM:
     case IceType_void:
       llvm::report_fatal_error("Unexpected bitcast.");
     case IceType_i1:
-      UnimplementedLoweringError(this, Inst);
+      UnimplementedLoweringError(this, Instr);
       break;
     case IceType_i8:
-      UnimplementedLoweringError(this, Inst);
+      UnimplementedLoweringError(this, Instr);
       break;
     case IceType_i16:
-      UnimplementedLoweringError(this, Inst);
+      UnimplementedLoweringError(this, Instr);
       break;
     case IceType_i32:
     case IceType_f32: {
       Variable *Src0R = legalizeToReg(Src0);
       Variable *T = makeReg(DestType);
       _mov(T, Src0R);
       lowerAssign(InstAssign::create(Func, Dest, T));
       break;
     }
     case IceType_i64: {
@@ skipping 26 matching lines @@
       lowerAssign(InstAssign::create(Func, Dest, T));
       break;
     }
     case IceType_v4i1:
     case IceType_v8i1:
     case IceType_v16i1:
     case IceType_v8i16:
     case IceType_v16i8:
     case IceType_v4f32:
     case IceType_v4i32: {
-      UnimplementedLoweringError(this, Inst);
+      UnimplementedLoweringError(this, Instr);
       break;
     }
     }
     break;
   }
   }
 }
 
-void TargetARM32::lowerExtractElement(const InstExtractElement *Inst) {
-  UnimplementedLoweringError(this, Inst);
+void TargetARM32::lowerExtractElement(const InstExtractElement *Instr) {
+  UnimplementedLoweringError(this, Instr);
 }
 
 namespace {
 // Validates FCMPARM32_TABLE's declaration w.r.t. InstFcmp::FCondition ordering
 // (and naming).
 enum {
 #define X(val, CC0, CC1) _fcmp_ll_##val,
   FCMPARM32_TABLE
 #undef X
       _fcmp_ll_NUM
@@ skipping 300 matching lines @@
   if (Srcs.swappedOperands()) {
     _cmp(ConstR, NonConstF);
   } else {
     Variable *T = makeReg(IceType_i32);
     _rsbs(T, ConstR, NonConstF);
     Context.insert<InstFakeUse>(T);
   }
   return CondWhenTrue(getIcmp32Mapping(Condition));
 }
 
-TargetARM32::CondWhenTrue TargetARM32::lowerIcmpCond(const InstIcmp *Inst) {
-  assert(Inst->getSrc(0)->getType() != IceType_i1);
-  assert(Inst->getSrc(1)->getType() != IceType_i1);
+TargetARM32::CondWhenTrue TargetARM32::lowerIcmpCond(const InstIcmp *Instr) {
+  assert(Instr->getSrc(0)->getType() != IceType_i1);
+  assert(Instr->getSrc(1)->getType() != IceType_i1);
 
-  Operand *Src0 = legalizeUndef(Inst->getSrc(0));
-  Operand *Src1 = legalizeUndef(Inst->getSrc(1));
+  Operand *Src0 = legalizeUndef(Instr->getSrc(0));
+  Operand *Src1 = legalizeUndef(Instr->getSrc(1));
 
-  const InstIcmp::ICond Condition = Inst->getCondition();
+  const InstIcmp::ICond Condition = Instr->getCondition();
   // a=icmp cond b, c ==>
   // GCC does:
   //   <u/s>xtb tb, b
   //   <u/s>xtb tc, c
   //   cmp      tb, tc
   //   mov.C1   t, #0
   //   mov.C2   t, #1
   //   mov      a, t
   // where the unsigned/sign extension is not needed for 32-bit. They also have
   // special cases for EQ and NE. E.g., for NE:
@@ skipping 22 matching lines @@
   case IceType_i8:
   case IceType_i16:
     return lowerInt8AndInt16IcmpCond(Condition, Src0, Src1);
   case IceType_i32:
     return lowerInt32IcmpCond(Condition, Src0, Src1);
   case IceType_i64:
     return lowerInt64IcmpCond(Condition, Src0, Src1);
   }
 }
 
-void TargetARM32::lowerIcmp(const InstIcmp *Inst) {
-  Variable *Dest = Inst->getDest();
+void TargetARM32::lowerIcmp(const InstIcmp *Instr) {
+  Variable *Dest = Instr->getDest();
 
   if (isVectorType(Dest->getType())) {
-    UnimplementedLoweringError(this, Inst);
+    UnimplementedLoweringError(this, Instr);
     return;
   }
 
   Operand *_0 =
       legalize(Ctx->getConstantZero(IceType_i32), Legal_Reg | Legal_Flex);
   Operand *_1 = legalize(Ctx->getConstantInt32(1), Legal_Reg | Legal_Flex);
   Variable *T = makeReg(IceType_i1);
 
   _mov(T, _0);
-  CondWhenTrue Cond = lowerIcmpCond(Inst);
+  CondWhenTrue Cond = lowerIcmpCond(Instr);
   _mov_redefined(T, _1, Cond.WhenTrue0);
   _mov(Dest, T);
 
   assert(Cond.WhenTrue1 == CondARM32::kNone);
 
   return;
 }
 
-void TargetARM32::lowerInsertElement(const InstInsertElement *Inst) {
-  UnimplementedLoweringError(this, Inst);
+void TargetARM32::lowerInsertElement(const InstInsertElement *Instr) {
+  UnimplementedLoweringError(this, Instr);
 }
 
 namespace {
 inline uint64_t getConstantMemoryOrder(Operand *Opnd) {
   if (auto *Integer = llvm::dyn_cast<ConstantInteger32>(Opnd))
     return Integer->getValue();
   return Intrinsics::MemoryOrderInvalid;
 }
 } // end of anonymous namespace
 
@@ skipping 688 matching lines @@
     }
   }
 
   if (Optimized) {
     *Reason = VarAssign;
   }
 
   return Optimized;
 }
 
-bool isAddOrSub(const Inst *Inst, InstArithmetic::OpKind *Kind) {
-  if (const auto *Arith = llvm::dyn_cast<InstArithmetic>(Inst)) {
+bool isAddOrSub(const Inst *Instr, InstArithmetic::OpKind *Kind) {
+  if (const auto *Arith = llvm::dyn_cast<InstArithmetic>(Instr)) {
     switch (Arith->getOp()) {
     default:
       return false;
     case InstArithmetic::Add:
     case InstArithmetic::Sub:
       *Kind = Arith->getOp();
       return true;
     }
   }
   return false;
@@ skipping 356 matching lines @@
 }
 
 void TargetARM32::randomlyInsertNop(float Probability,
                                     RandomNumberGenerator &RNG) {
   RandomNumberGeneratorWrapper RNGW(RNG);
   if (RNGW.getTrueWithProbability(Probability)) {
     UnimplementedError(Func->getContext()->getFlags());
   }
 }
 
-void TargetARM32::lowerPhi(const InstPhi * /*Inst*/) {
+void TargetARM32::lowerPhi(const InstPhi * /*Instr*/) {
   Func->setError("Phi found in regular instruction list");
 }
 
-void TargetARM32::lowerRet(const InstRet *Inst) {
+void TargetARM32::lowerRet(const InstRet *Instr) {
   Variable *Reg = nullptr;
-  if (Inst->hasRetValue()) {
-    Operand *Src0 = Inst->getRetValue();
+  if (Instr->hasRetValue()) {
+    Operand *Src0 = Instr->getRetValue();
     Type Ty = Src0->getType();
     if (Ty == IceType_i64) {
       Src0 = legalizeUndef(Src0);
       Variable *R0 = legalizeToReg(loOperand(Src0), RegARM32::Reg_r0);
       Variable *R1 = legalizeToReg(hiOperand(Src0), RegARM32::Reg_r1);
       Reg = R0;
       Context.insert<InstFakeUse>(R1);
     } else if (Ty == IceType_f32) {
       Variable *S0 = legalizeToReg(Src0, RegARM32::Reg_s0);
       Reg = S0;
@@ skipping 16 matching lines @@
   _ret(getPhysicalRegister(RegARM32::Reg_lr), Reg);
 
   // Add a fake use of sp to make sure sp stays alive for the entire function.
   // Otherwise post-call sp adjustments get dead-code eliminated.
   // TODO: Are there more places where the fake use should be inserted? E.g.
   // "void f(int n){while(1) g(n);}" may not have a ret instruction.
   Variable *SP = getPhysicalRegister(RegARM32::Reg_sp);
   Context.insert<InstFakeUse>(SP);
 }
 
-void TargetARM32::lowerSelect(const InstSelect *Inst) {
-  Variable *Dest = Inst->getDest();
+void TargetARM32::lowerSelect(const InstSelect *Instr) {
+  Variable *Dest = Instr->getDest();
   Type DestTy = Dest->getType();
-  Operand *SrcT = Inst->getTrueOperand();
-  Operand *SrcF = Inst->getFalseOperand();
-  Operand *Condition = Inst->getCondition();
+  Operand *SrcT = Instr->getTrueOperand();
+  Operand *SrcF = Instr->getFalseOperand();
+  Operand *Condition = Instr->getCondition();
 
   if (isVectorType(DestTy)) {
-    UnimplementedLoweringError(this, Inst);
+    UnimplementedLoweringError(this, Instr);
     return;
   }
 
   lowerInt1ForSelect(Dest, Condition, legalizeUndef(SrcT), legalizeUndef(SrcF));
 }
 
-void TargetARM32::lowerStore(const InstStore *Inst) {
-  Operand *Value = Inst->getData();
-  Operand *Addr = Inst->getAddr();
+void TargetARM32::lowerStore(const InstStore *Instr) {
+  Operand *Value = Instr->getData();
+  Operand *Addr = Instr->getAddr();
   OperandARM32Mem *NewAddr = formMemoryOperand(Addr, Value->getType());
   Type Ty = NewAddr->getType();
 
   if (Ty == IceType_i64) {
     Value = legalizeUndef(Value);
     Variable *ValueHi = legalizeToReg(hiOperand(Value));
     Variable *ValueLo = legalizeToReg(loOperand(Value));
     _str(ValueHi, llvm::cast<OperandARM32Mem>(hiOperand(NewAddr)));
     _str(ValueLo, llvm::cast<OperandARM32Mem>(loOperand(NewAddr)));
   } else {
     Variable *ValueR = legalizeToReg(Value);
     _str(ValueR, NewAddr);
   }
 }
 
 void TargetARM32::doAddressOptStore() {
   Inst *Instr = Context.getCur();
   assert(llvm::isa<InstStore>(Instr));
   Operand *Src = Instr->getSrc(0);
   Operand *Addr = Instr->getSrc(1);
   if (OperandARM32Mem *Mem =
           formAddressingMode(Src->getType(), Func, Instr, Addr)) {
     Instr->setDeleted();
     Context.insert<InstStore>(Src, Mem);
   }
 }
 
-void TargetARM32::lowerSwitch(const InstSwitch *Inst) {
+void TargetARM32::lowerSwitch(const InstSwitch *Instr) {
   // This implements the most naive possible lowering.
   // cmp a,val[0]; jeq label[0]; cmp a,val[1]; jeq label[1]; ... jmp default
-  Operand *Src0 = Inst->getComparison();
-  SizeT NumCases = Inst->getNumCases();
+  Operand *Src0 = Instr->getComparison();
+  SizeT NumCases = Instr->getNumCases();
   if (Src0->getType() == IceType_i64) {
     Src0 = legalizeUndef(Src0);
     Variable *Src0Lo = legalizeToReg(loOperand(Src0));
     Variable *Src0Hi = legalizeToReg(hiOperand(Src0));
     for (SizeT I = 0; I < NumCases; ++I) {
-      Operand *ValueLo = Ctx->getConstantInt32(Inst->getValue(I));
-      Operand *ValueHi = Ctx->getConstantInt32(Inst->getValue(I) >> 32);
+      Operand *ValueLo = Ctx->getConstantInt32(Instr->getValue(I));
+      Operand *ValueHi = Ctx->getConstantInt32(Instr->getValue(I) >> 32);
       ValueLo = legalize(ValueLo, Legal_Reg | Legal_Flex);
       ValueHi = legalize(ValueHi, Legal_Reg | Legal_Flex);
       _cmp(Src0Lo, ValueLo);
       _cmp(Src0Hi, ValueHi, CondARM32::EQ);
-      _br(Inst->getLabel(I), CondARM32::EQ);
+      _br(Instr->getLabel(I), CondARM32::EQ);
     }
-    _br(Inst->getLabelDefault());
+    _br(Instr->getLabelDefault());
     return;
   }
 
   Variable *Src0Var = legalizeToReg(Src0);
   // If Src0 is not an i32, we left shift it -- see the icmp lowering for the
   // reason.
   assert(Src0Var->mustHaveReg());
   const size_t ShiftAmt = 32 - getScalarIntBitWidth(Src0->getType());
   assert(ShiftAmt < 32);
   if (ShiftAmt > 0) {
     Operand *ShAmtImm = shAmtImm(ShiftAmt);
     Variable *T = makeReg(IceType_i32);
     _lsl(T, Src0Var, ShAmtImm);
     Src0Var = T;
   }
 
   for (SizeT I = 0; I < NumCases; ++I) {
-    Operand *Value = Ctx->getConstantInt32(Inst->getValue(I) << ShiftAmt);
+    Operand *Value = Ctx->getConstantInt32(Instr->getValue(I) << ShiftAmt);
     Value = legalize(Value, Legal_Reg | Legal_Flex);
     _cmp(Src0Var, Value);
-    _br(Inst->getLabel(I), CondARM32::EQ);
+    _br(Instr->getLabel(I), CondARM32::EQ);
   }
-  _br(Inst->getLabelDefault());
+  _br(Instr->getLabelDefault());
 }
 
-void TargetARM32::lowerUnreachable(const InstUnreachable * /*Inst*/) {
+void TargetARM32::lowerUnreachable(const InstUnreachable * /*Instr*/) {
   _trap();
 }
 
 void TargetARM32::prelowerPhis() {
   PhiLowering::prelowerPhis32Bit<TargetARM32>(this, Context.getNode(), Func);
 }
 
 Variable *TargetARM32::makeVectorOfZeros(Type Ty, int32_t RegNum) {
   Variable *Reg = makeReg(Ty, RegNum);
   Context.insert<InstFakeDef>(Reg);
@@ skipping 1060 matching lines @@
   Str << ".eabi_attribute 14, 3   @ Tag_ABI_PCS_R9_use: Not used\n";
 }
 
 llvm::SmallBitVector TargetARM32::TypeToRegisterSet[RegARM32::RCARM32_NUM];
 llvm::SmallBitVector
     TargetARM32::TypeToRegisterSetUnfiltered[RegARM32::RCARM32_NUM];
 llvm::SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM];
 
 } // end of namespace ARM32
 } // end of namespace Ice