Subzero. ARM32. Nonsfi.

tests_lit/llvm2ice_tests/nonsfi.ll

Index: tests_lit/llvm2ice_tests/nonsfi.ll
diff --git a/tests_lit/llvm2ice_tests/nonsfi.ll b/tests_lit/llvm2ice_tests/nonsfi.ll
index 5b80c42b64ebbb3c3a246da739aa2c280cda5c16..0af3036d1d36351950593b6348e6874000857ec2 100644
--- a/tests_lit/llvm2ice_tests/nonsfi.ll
+++ b/tests_lit/llvm2ice_tests/nonsfi.ll
@@ -1,10 +1,14 @@
-; RUN: %p2i -i %s --filetype=obj --assemble --disassemble --args -O2 -nonsfi=1 \
-; RUN:   --ffunction-sections \
+; RUN: %p2i -i %s --target=x8632 --filetype=obj --assemble --disassemble \
+; RUN:   --args -O2 -nonsfi=1 --ffunction-sections \
 ; RUN:   | FileCheck --check-prefix=NONSFI %s
-; RUN: %p2i -i %s --filetype=obj --assemble --disassemble --args -O2 -nonsfi=0 \
-; RUN:   --ffunction-sections \
+; RUN: %p2i -i %s --target=x8632 --filetype=obj --assemble --disassemble \
+; RUN:   --args -O2 -nonsfi=0 --ffunction-sections \
 ; RUN:   | FileCheck --check-prefix=DEFAULT %s
 
+; RUN: %p2i -i %s --target=arm32 --filetype=obj --assemble --disassemble \
+; RUN:   --args -O2 -nonsfi=1 --ffunction-sections \
+; RUN:   | FileCheck --check-prefix=ARM32-NONSFI %s
+
 @G1 = internal global [4 x i8] zeroinitializer, align 4
 @G2 = internal global [4 x i8] zeroinitializer, align 4
 
@@ -20,6 +24,9 @@ entry:
 ; NONSFI: call {{.*}} R_386_PC32 {{.*}}testLoadBasic
 ; DEFAULT-LABEL: testCallRegular
 
+; ARM32-NONSFI-LABEL: testCallRegular
+; ARM32-NONSFI: bl {{.*}} <testCallRegular> {{.*}} R_ARM_CALL
+
 define internal double @testCallBuiltin(double %val) {
 entry:
   %result = frem double %val, %val
@@ -30,6 +37,9 @@ entry:
 ; NONSFI: call {{.*}} R_386_PC32 fmod
 ; DEFAULT-LABEL: testCallBuiltin
 
+; ARM32-NONSFI-LABEL: testCallBuiltin
+; ARM32-NONSFI: bl {{.*}} <fmod> {{.*}} R_ARM_CALL
+
 define internal i32 @testLoadBasic() {
 entry:
   %a = bitcast [4 x i8]* @G1 to i32*
@@ -41,6 +51,14 @@ entry:
 ; NONSFI: mov {{.*}} R_386_GOTOFF {{G1|.bss}}
 ; DEFAULT-LABEL: testLoadBasic
 
+; ARM32 PIC load.
+; ARM32-NONSFI-LABEL: testLoadBasic
+; ARM32-NONSFI:      movw {{.*}} R_ARM_MOVW_PREL_NC _GLOBAL_OFFSET_TABLE_
+; ARM32-NONSFI-NEXT: movt {{.*}} R_ARM_MOVT_PREL _GLOBAL_OFFSET_TABLE_
+; ARM32-NONSFI:      movw [[REG:r[0-9]+]], {{.*}} R_ARM_MOVW_PREL_NC {{.*}}G1
+; ARM32-NONSFI-NEXT: movt [[REG]], {{.*}} R_ARM_MOVT_PREL {{.*}}G1
+; ARM32-NONSFI-NEXT: ldr r{{[0-9]+}}, [pc, [[REG]]]
+
 define internal i32 @testLoadFixedOffset() {
 entry:
   %a = ptrtoint [4 x i8]* @G1 to i32
@@ -54,6 +72,15 @@ entry:
 ; NONSFI: mov {{.*}}+0x4] {{.*}} R_386_GOTOFF {{G1|.bss}}
 ; DEFAULT-LABEL: testLoadFixedOffset
 
+; ARM32-NONSFI-LABEL: testLoadFixedOffset
+; ARM32-NONSFI:      movw [[GOT:r[0-9]+]], {{.*}} R_ARM_MOVW_PREL_NC _GLOBAL_OFFSET_TABLE_
+; ARM32-NONSFI-NEXT: movt [[GOT]], {{.*}} R_ARM_MOVT_PREL _GLOBAL_OFFSET_TABLE_
+; ARM32-NONSFI:      movw [[REG:r[0-9]+]], {{.*}} R_ARM_MOVW_PREL_NC {{.*}}G1
+; ARM32-NONSFI-NEXT: movt [[REG]], {{.*}} R_ARM_MOVT_PREL {{.*}}G1
+; ARM32-NONSFI-NEXT: ldr [[ADDR:r[0-9]+]], [pc, [[REG]]]
+; ARM32-NONSFI-NEXT: add [[G1BASE:r[0-9]+]], [[GOT]], [[ADDR]]
+; ARM32-NONSFI-NEXT: add {{.*}}, [[G1BASE]], #4
+
 define internal i32 @testLoadIndexed(i32 %idx) {
 entry:
   %a = ptrtoint [4 x i8]* @G1 to i32
@@ -70,6 +97,15 @@ entry:
 ; NONSFI: mov {{.*}}*4+0xc] {{.*}} R_386_GOTOFF {{G1|.bss}}
 ; DEFAULT-LABEL: testLoadIndexed
 
+; ARM32-NONSFI-LABEL: testLoadIndexed
+; ARM32-NONSFI:      movw [[GOT:r[0-9]+]], {{.*}} R_ARM_MOVW_PREL_NC _GLOBAL_OFFSET_TABLE_
+; ARM32-NONSFI-NEXT: movt [[GOT]], {{.*}} R_ARM_MOVT_PREL _GLOBAL_OFFSET_TABLE_
+; ARM32-NONSFI:      movw [[REG:r[0-9]+]], {{.*}} R_ARM_MOVW_PREL_NC {{.*}}G1
+; ARM32-NONSFI-NEXT: movt [[REG]], {{.*}} R_ARM_MOVT_PREL {{.*}}G1
+; ARM32-NONSFI-NEXT: ldr [[ADDR:r[0-9]+]], [pc, [[REG]]]
+; ARM32-NONSFI-NEXT: add [[G1BASE:r[0-9]+]], [[GOT]], [[ADDR]]
+; ARaM32-NONSFI-NEXT: add {{.*}}, [[G1BASE]]
+
 define internal i32 @testLoadIndexedBase(i32 %base, i32 %idx) {
 entry:
   %a = ptrtoint [4 x i8]* @G1 to i32