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1 ; RUN: %p2i -i %s --filetype=obj --assemble --disassemble --args -O2 -nonsfi=1 \ | 1 ; RUN: %p2i -i %s --target=x8632 --filetype=obj --assemble --disassemble \ |
2 ; RUN: --ffunction-sections \ | 2 ; RUN: --args -O2 -nonsfi=1 --ffunction-sections \ |
3 ; RUN: | FileCheck --check-prefix=NONSFI %s | 3 ; RUN: | FileCheck --check-prefix=NONSFI %s |
4 ; RUN: %p2i -i %s --filetype=obj --assemble --disassemble --args -O2 -nonsfi=0 \ | 4 ; RUN: %p2i -i %s --target=x8632 --filetype=obj --assemble --disassemble \ |
5 ; RUN: --ffunction-sections \ | 5 ; RUN: --args -O2 -nonsfi=0 --ffunction-sections \ |
6 ; RUN: | FileCheck --check-prefix=DEFAULT %s | 6 ; RUN: | FileCheck --check-prefix=DEFAULT %s |
7 | 7 |
| 8 ; RUN: %p2i -i %s --target=arm32 --filetype=obj --assemble --disassemble \ |
| 9 ; RUN: --args -O2 -nonsfi=1 --ffunction-sections \ |
| 10 ; RUN: | FileCheck --check-prefix=ARM32-NONSFI %s |
| 11 |
8 @G1 = internal global [4 x i8] zeroinitializer, align 4 | 12 @G1 = internal global [4 x i8] zeroinitializer, align 4 |
9 @G2 = internal global [4 x i8] zeroinitializer, align 4 | 13 @G2 = internal global [4 x i8] zeroinitializer, align 4 |
10 | 14 |
11 define internal void @testCallRegular() { | 15 define internal void @testCallRegular() { |
12 entry: | 16 entry: |
13 ; Make a call to a *different* function, plus use -ffunction-sections, to | 17 ; Make a call to a *different* function, plus use -ffunction-sections, to |
14 ; force an appropriately-named relocation. | 18 ; force an appropriately-named relocation. |
15 call i32 @testLoadBasic() | 19 call i32 @testLoadBasic() |
16 ret void | 20 ret void |
17 } | 21 } |
18 ; Expect a simple direct call to testCallRegular. | 22 ; Expect a simple direct call to testCallRegular. |
19 ; NONSFI-LABEL: testCallRegular | 23 ; NONSFI-LABEL: testCallRegular |
20 ; NONSFI: call {{.*}} R_386_PC32 {{.*}}testLoadBasic | 24 ; NONSFI: call {{.*}} R_386_PC32 {{.*}}testLoadBasic |
21 ; DEFAULT-LABEL: testCallRegular | 25 ; DEFAULT-LABEL: testCallRegular |
22 | 26 |
| 27 ; ARM32-NONSFI-LABEL: testCallRegular |
| 28 ; ARM32-NONSFI: movw [[REG:r[0-9]+]], {{.*}} R_ARM_MOVW_PREL_NC GOTOFF{{.*}
}testLoadBasic |
| 29 ; ARM32-NONSFI-NEXT: movt [[REG:r[0-9]+]], {{.*}} R_ARM_MOVT_PREL GOTOFF{{.*}}te
stLoadBasic |
| 30 ; ARM32-NONSFI-NEXT: ldr [[GOTOFF:r[0-9]+]], [pc, [[REG]]] |
| 31 ; ARM32-NONSFI-NEXT: add [[CT:r[0-9]+]], {{.*}}, [[CT]] |
| 32 ; ARM32-NONSFI: blx [[CT]] |
| 33 |
23 define internal double @testCallBuiltin(double %val) { | 34 define internal double @testCallBuiltin(double %val) { |
24 entry: | 35 entry: |
25 %result = frem double %val, %val | 36 %result = frem double %val, %val |
26 ret double %result | 37 ret double %result |
27 } | 38 } |
28 ; Expect a simple direct call to fmod. | 39 ; Expect a simple direct call to fmod. |
29 ; NONSFI-LABEL: testCallBuiltin | 40 ; NONSFI-LABEL: testCallBuiltin |
30 ; NONSFI: call {{.*}} R_386_PC32 fmod | 41 ; NONSFI: call {{.*}} R_386_PC32 fmod |
31 ; DEFAULT-LABEL: testCallBuiltin | 42 ; DEFAULT-LABEL: testCallBuiltin |
32 | 43 |
| 44 ; ARM32-NONSFI-LABEL: testCallBuiltin |
| 45 ; ARM32-NONSFI: movw [[REG:r[0-9]+]], {{.*}} R_ARM_MOVW_PREL_NC GOTOFF{{.*}
}fmod |
| 46 ; ARM32-NONSFI-NEXT: movt [[REG:r[0-9]+]], {{.*}} R_ARM_MOVT_PREL GOTOFF{{.*}}fm
od |
| 47 ; ARM32-NONSFI-NEXT: ldr [[GOTOFF:r[0-9]+]], [pc, [[REG]]] |
| 48 ; ARM32-NONSFI-NEXT: add [[CT:r[0-9]+]], {{.*}}, [[CT]] |
| 49 ; ARM32-NONSFI: blx [[CT]] |
| 50 |
33 define internal i32 @testLoadBasic() { | 51 define internal i32 @testLoadBasic() { |
34 entry: | 52 entry: |
35 %a = bitcast [4 x i8]* @G1 to i32* | 53 %a = bitcast [4 x i8]* @G1 to i32* |
36 %b = load i32, i32* %a, align 1 | 54 %b = load i32, i32* %a, align 1 |
37 ret i32 %b | 55 ret i32 %b |
38 } | 56 } |
39 ; Expect a load with a R_386_GOTOFF relocation. | 57 ; Expect a load with a R_386_GOTOFF relocation. |
40 ; NONSFI-LABEL: testLoadBasic | 58 ; NONSFI-LABEL: testLoadBasic |
41 ; NONSFI: mov {{.*}} R_386_GOTOFF {{G1|.bss}} | 59 ; NONSFI: mov {{.*}} R_386_GOTOFF {{G1|.bss}} |
42 ; DEFAULT-LABEL: testLoadBasic | 60 ; DEFAULT-LABEL: testLoadBasic |
43 | 61 |
| 62 ; ARM32 PIC load. |
| 63 ; ARM32-NONSFI-LABEL: testLoadBasic |
| 64 ; ARM32-NONSFI: movw {{.*}} R_ARM_MOVW_PREL_NC _GLOBAL_OFFSET_TABLE_ |
| 65 ; ARM32-NONSFI-NEXT: movt {{.*}} R_ARM_MOVT_PREL _GLOBAL_OFFSET_TABLE_ |
| 66 ; ARM32-NONSFI: movw [[REG:r[0-9]+]], {{.*}} R_ARM_MOVW_PREL_NC {{.*}}G1 |
| 67 ; ARM32-NONSFI-NEXT: movt [[REG]], {{.*}} R_ARM_MOVT_PREL {{.*}}G1 |
| 68 ; ARM32-NONSFI-NEXT: ldr r{{[0-9]+}}, [pc, [[REG]]] |
| 69 |
44 define internal i32 @testLoadFixedOffset() { | 70 define internal i32 @testLoadFixedOffset() { |
45 entry: | 71 entry: |
46 %a = ptrtoint [4 x i8]* @G1 to i32 | 72 %a = ptrtoint [4 x i8]* @G1 to i32 |
47 %a1 = add i32 %a, 4 | 73 %a1 = add i32 %a, 4 |
48 %a2 = inttoptr i32 %a1 to i32* | 74 %a2 = inttoptr i32 %a1 to i32* |
49 %b = load i32, i32* %a2, align 1 | 75 %b = load i32, i32* %a2, align 1 |
50 ret i32 %b | 76 ret i32 %b |
51 } | 77 } |
52 ; Expect a load with a R_386_GOTOFF relocation plus an immediate offset. | 78 ; Expect a load with a R_386_GOTOFF relocation plus an immediate offset. |
53 ; NONSFI-LABEL: testLoadFixedOffset | 79 ; NONSFI-LABEL: testLoadFixedOffset |
54 ; NONSFI: mov {{.*}}+0x4] {{.*}} R_386_GOTOFF {{G1|.bss}} | 80 ; NONSFI: mov {{.*}}+0x4] {{.*}} R_386_GOTOFF {{G1|.bss}} |
55 ; DEFAULT-LABEL: testLoadFixedOffset | 81 ; DEFAULT-LABEL: testLoadFixedOffset |
56 | 82 |
| 83 ; ARM32-NONSFI-LABEL: testLoadFixedOffset |
| 84 ; ARM32-NONSFI: movw [[GOT:r[0-9]+]], {{.*}} R_ARM_MOVW_PREL_NC _GLOBAL_OFF
SET_TABLE_ |
| 85 ; ARM32-NONSFI-NEXT: movt [[GOT]], {{.*}} R_ARM_MOVT_PREL _GLOBAL_OFFSET_TABLE_ |
| 86 ; ARM32-NONSFI: movw [[REG:r[0-9]+]], {{.*}} R_ARM_MOVW_PREL_NC {{.*}}G1 |
| 87 ; ARM32-NONSFI-NEXT: movt [[REG]], {{.*}} R_ARM_MOVT_PREL {{.*}}G1 |
| 88 ; ARM32-NONSFI-NEXT: ldr [[ADDR:r[0-9]+]], [pc, [[REG]]] |
| 89 ; ARM32-NONSFI-NEXT: add [[G1BASE:r[0-9]+]], [[GOT]], [[ADDR]] |
| 90 ; ARM32-NONSFI-NEXT: add {{.*}}, [[G1BASE]], #4 |
| 91 |
57 define internal i32 @testLoadIndexed(i32 %idx) { | 92 define internal i32 @testLoadIndexed(i32 %idx) { |
58 entry: | 93 entry: |
59 %a = ptrtoint [4 x i8]* @G1 to i32 | 94 %a = ptrtoint [4 x i8]* @G1 to i32 |
60 %a0 = mul i32 %idx, 4 | 95 %a0 = mul i32 %idx, 4 |
61 %a1 = add i32 %a0, 12 | 96 %a1 = add i32 %a0, 12 |
62 %a2 = add i32 %a1, %a | 97 %a2 = add i32 %a1, %a |
63 %a3 = inttoptr i32 %a2 to i32* | 98 %a3 = inttoptr i32 %a2 to i32* |
64 %b = load i32, i32* %a3, align 1 | 99 %b = load i32, i32* %a3, align 1 |
65 ret i32 %b | 100 ret i32 %b |
66 } | 101 } |
67 ; Expect a load with a R_386_GOTOFF relocation plus an immediate offset, plus a | 102 ; Expect a load with a R_386_GOTOFF relocation plus an immediate offset, plus a |
68 ; scaled index register. | 103 ; scaled index register. |
69 ; NONSFI-LABEL: testLoadIndexed | 104 ; NONSFI-LABEL: testLoadIndexed |
70 ; NONSFI: mov {{.*}}*4+0xc] {{.*}} R_386_GOTOFF {{G1|.bss}} | 105 ; NONSFI: mov {{.*}}*4+0xc] {{.*}} R_386_GOTOFF {{G1|.bss}} |
71 ; DEFAULT-LABEL: testLoadIndexed | 106 ; DEFAULT-LABEL: testLoadIndexed |
72 | 107 |
| 108 ; ARM32-NONSFI-LABEL: testLoadIndexed |
| 109 ; ARM32-NONSFI: movw [[GOT:r[0-9]+]], {{.*}} R_ARM_MOVW_PREL_NC _GLOBAL_OFF
SET_TABLE_ |
| 110 ; ARM32-NONSFI-NEXT: movt [[GOT]], {{.*}} R_ARM_MOVT_PREL _GLOBAL_OFFSET_TABLE_ |
| 111 ; ARM32-NONSFI: movw [[REG:r[0-9]+]], {{.*}} R_ARM_MOVW_PREL_NC {{.*}}G1 |
| 112 ; ARM32-NONSFI-NEXT: movt [[REG]], {{.*}} R_ARM_MOVT_PREL {{.*}}G1 |
| 113 ; ARM32-NONSFI-NEXT: ldr [[ADDR:r[0-9]+]], [pc, [[REG]]] |
| 114 ; ARM32-NONSFI-NEXT: add [[G1BASE:r[0-9]+]], [[GOT]], [[ADDR]] |
| 115 ; ARaM32-NONSFI-NEXT: add {{.*}}, [[G1BASE]] |
| 116 |
73 define internal i32 @testLoadIndexedBase(i32 %base, i32 %idx) { | 117 define internal i32 @testLoadIndexedBase(i32 %base, i32 %idx) { |
74 entry: | 118 entry: |
75 %a = ptrtoint [4 x i8]* @G1 to i32 | 119 %a = ptrtoint [4 x i8]* @G1 to i32 |
76 %a0 = mul i32 %idx, 4 | 120 %a0 = mul i32 %idx, 4 |
77 %a1 = add i32 %a0, %base | 121 %a1 = add i32 %a0, %base |
78 %a2 = add i32 %a1, %a | 122 %a2 = add i32 %a1, %a |
79 %a3 = add i32 %a2, 12 | 123 %a3 = add i32 %a2, 12 |
80 %a4 = inttoptr i32 %a3 to i32* | 124 %a4 = inttoptr i32 %a3 to i32* |
81 %b = load i32, i32* %a4, align 1 | 125 %b = load i32, i32* %a4, align 1 |
82 ret i32 %b | 126 ret i32 %b |
(...skipping 27 matching lines...) Expand all Loading... |
110 %a = bitcast [4 x i8]* @G1 to i32* | 154 %a = bitcast [4 x i8]* @G1 to i32* |
111 %b = load i32, i32* %a, align 1 | 155 %b = load i32, i32* %a, align 1 |
112 %c = add i32 %b, 1234 | 156 %c = add i32 %b, 1234 |
113 store i32 %c, i32* %a, align 1 | 157 store i32 %c, i32* %a, align 1 |
114 ret void | 158 ret void |
115 } | 159 } |
116 ; Expect an RMW optimization with a R_386_GOTOFF relocation. | 160 ; Expect an RMW optimization with a R_386_GOTOFF relocation. |
117 ; NONSFI-LABEL: testRMW | 161 ; NONSFI-LABEL: testRMW |
118 ; NONSFI: add DWORD PTR {{.*}}+0x0],0x4d2 {{.*}} R_386_GOTOFF {{G1|.bss}} | 162 ; NONSFI: add DWORD PTR {{.*}}+0x0],0x4d2 {{.*}} R_386_GOTOFF {{G1|.bss}} |
119 ; DEFAULT-LABEL: testRMW | 163 ; DEFAULT-LABEL: testRMW |
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