Subzero. ARM32. Nonsfi.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 591 matching lines @@
 
 namespace Ice {
 namespace ARM32 {
 
 size_t MoveRelocatableFixup::emit(GlobalContext *Ctx,
                                   const Assembler &Asm) const {
   if (!BuildDefs::dump())
     return InstARM32::InstSize;
   Ostream &Str = Ctx->getStrEmit();
   IValueT Inst = Asm.load<IValueT>(position());
+  const bool IsMovw = kind() == llvm::ELF::R_ARM_MOVW_ABS_NC ||
+                      kind() == llvm::ELF::R_ARM_MOVW_PREL_NC;
   Str << "\t"
-         "mov" << (kind() == llvm::ELF::R_ARM_MOVW_ABS_NC ? "w" : "t") << "\t"
+         "mov" << (IsMovw ? "w" : "t") << "\t"
       << RegARM32::getRegName(RegNumT::fixme((Inst >> kRdShift) & 0xF))
-      << ", #:" << (kind() == llvm::ELF::R_ARM_MOVW_ABS_NC ? "lower" : "upper")
-      << "16:" << symbol(Ctx, &Asm) << "\t@ .word "
-      << llvm::format_hex_no_prefix(Inst, 8) << "\n";
+      << ", #:" << (IsMovw ? "lower" : "upper") << "16:" << symbol(Ctx, &Asm)
+      << "\t@ .word " << llvm::format_hex_no_prefix(Inst, 8) << "\n";
   return InstARM32::InstSize;
 }
 
 // This fixup points to an ARM32 instruction with the following format:
 void MoveRelocatableFixup::emitOffset(Assembler *Asm) const {
   // cccc00110T00iiiiddddiiiiiiiiiiii where cccc=Cond, dddd=Rd,
   // iiiiiiiiiiiiiiii = Imm16, and T=1 for movt.
 
   const IValueT Inst = Asm->load<IValueT>(position());
   constexpr IValueT Imm16Mask = 0x000F0FFF;
-  const IValueT Imm16 =
-      offset() >> (kind() == llvm::ELF::R_ARM_MOVW_ABS_NC ? 0 : 16) & 0xffff;
+  const IValueT Imm16 = offset() & 0xffff;
   Asm->store(position(),
              (Inst & ~Imm16Mask) | ((Imm16 >> 12) << 16) | (Imm16 & 0xfff));
 }
 
 MoveRelocatableFixup *AssemblerARM32::createMoveFixup(bool IsMovW,
                                                       const Constant *Value) {
   MoveRelocatableFixup *F =
       new (allocate<MoveRelocatableFixup>()) MoveRelocatableFixup();
-  F->set_kind(IsMovW ? llvm::ELF::R_ARM_MOVW_ABS_NC
-                     : llvm::ELF::R_ARM_MOVT_ABS);
+  F->set_kind(IsMovW ? (IsNonsfi ? llvm::ELF::R_ARM_MOVW_PREL_NC
+                                 : llvm::ELF::R_ARM_MOVW_ABS_NC)
+                     : (IsNonsfi ? llvm::ELF::R_ARM_MOVT_PREL
+                                 : llvm::ELF::R_ARM_MOVT_ABS));
   F->set_value(Value);
   Buffer.installFixup(F);
   return F;
 }
 
 size_t BlRelocatableFixup::emit(GlobalContext *Ctx,
                                 const Assembler &Asm) const {
   if (!BuildDefs::dump())
     return InstARM32::InstSize;
   Ostream &Str = Ctx->getStrEmit();
@@ skipping 2495 matching lines @@
   constexpr const char *Vsqrts = "vsqrts";
   IValueT Sd = encodeSRegister(OpSd, "Sd", Vsqrts);
   IValueT Sm = encodeSRegister(OpSm, "Sm", Vsqrts);
   constexpr IValueT VsqrtsOpcode = B23 | B21 | B20 | B16 | B7 | B6;
   constexpr IValueT S0 = 0;
   emitVFPsss(Cond, VsqrtsOpcode, Sd, S0, Sm);
 }
 
 } // end of namespace ARM32
 } // end of namespace Ice