Fix vector load/stores in the ARM assembler.

src/IceAssemblerARM32.h

 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 55 matching lines @@
 
 public:
   // Rotation values.
   enum RotationValue {
     kRotateNone, // Omitted
     kRotate8,    // ror #8
     kRotate16,   // ror #16
     kRotate24    // ror #24
   };
 
+  // Encoding of the number of D registers in a list of D registers.
+  enum DRegListSize {
+    DRegListSize1 = 7,  // 0b0111
+    DRegListSize2 = 10, // 0b1010
+    DRegListSIze3 = 6,  // 0b0110
+    DRegListSize4 = 2   // 0b0010
+  };
+
   class TargetInfo {
     TargetInfo(const TargetInfo &) = delete;
     TargetInfo &operator=(const TargetInfo &) = delete;
 
   public:
     TargetInfo(bool HasFramePointer, SizeT FrameOrStackReg)
         : HasFramePointer(HasFramePointer), FrameOrStackReg(FrameOrStackReg) {}
     explicit TargetInfo(const TargetLowering *Target)
         : HasFramePointer(Target->hasFramePointer()),
           FrameOrStackReg(Target->getFrameOrStackReg()) {}
@@ skipping 306 matching lines @@
 
   void vldrs(const Operand *OpSd, const Operand *OpAddress,
              CondARM32::Cond Cond, const TargetInfo &TInfo);
 
   void vldrs(const Operand *OpSd, const Operand *OpAddress,
              CondARM32::Cond Cond, const TargetLowering *Lowering) {
     const TargetInfo TInfo(Lowering);
     vldrs(OpSd, OpAddress, Cond, TInfo);
   }
 
+  // ElmtSize = #bits in vector element.
+  void vld1qr(size_t ElmtSize, const Operand *OpQd, const Operand *OpRn,
+              const TargetInfo &TInfo);
+
+  void vld1qr(size_t ElmtSize, const Operand *OpQd, const Operand *OpRn,
+              const TargetLowering *Lowering) {
+    const TargetInfo TInfo(Lowering);
+    vld1qr(ElmtSize, OpQd, OpRn, TInfo);
+  }
+
   void vmovd(const Operand *OpDn, const OperandARM32FlexFpImm *OpFpImm,
              CondARM32::Cond Cond);
 
   void vmovdd(const Operand *OpDd, const Variable *OpDm, CondARM32::Cond Cond);
 
   void vmovdrr(const Operand *OpDm, const Operand *OpRt, const Operand *OpRt2,
                CondARM32::Cond Cond);
 
   void vmovrrd(const Operand *OpRt, const Operand *OpRt2, const Operand *OpDm,
                CondARM32::Cond Cond);
@@ skipping 58 matching lines @@
 
   void vstrs(const Operand *OpSd, const Operand *OpAddress,
              CondARM32::Cond Cond, const TargetInfo &TInfo);
 
   void vstrs(const Operand *OpSd, const Operand *OpAddress,
              CondARM32::Cond Cond, const TargetLowering *Lowering) {
     const TargetInfo TInfo(Lowering);
     vstrs(OpSd, OpAddress, Cond, TInfo);
   }
 
+  // ElmtSize = #bits in vector element.
+  void vst1qr(size_t ElmtSize, const Operand *OpQd, const Operand *OpAddress,
+              const TargetInfo &TInfo);
+
+  void vst1qr(size_t ElmtSize, const Operand *OpQd, const Operand *OpRn,
+              const TargetLowering *Lowering) {
+    const TargetInfo TInfo(Lowering);
+    vst1qr(ElmtSize, OpQd, OpRn, TInfo);
+  }
+
   void vsubd(const Operand *OpDd, const Operand *OpDn, const Operand *OpDm,
              CondARM32::Cond Cond);
 
   // Integer vector subtract.
   void vsubqi(Type ElmtTy, const Operand *OpQd, const Operand *OpQm,
               const Operand *OpQn);
 
   // Float vector subtract
   void vsubqf(const Operand *OpQd, const Operand *OpQm, const Operand *OpQn);
 
@@ skipping 104 matching lines @@
                     const Variable *OpBaseReg, SizeT NumConsecRegs);
 
   // Pattern cccc111xxDxxxxxxdddd101xxxMxmmmm where cccc=Cond, ddddD=Sd,
   // Mmmmm=Dm, and xx0xxxxxxdddd000xxx0x0000=Opcode.
   void emitVFPsd(CondARM32::Cond Cond, IValueT Opcode, IValueT Sd, IValueT Dm);
 
   // Pattern cccc111xxDxxxxxxdddd101xxxMxmmmm where cccc=Cond, Ddddd=Dd,
   // mmmmM=Sm, and xx0xxxxxxdddd000xxx0x0000=Opcode.
   void emitVFPds(CondARM32::Cond Cond, IValueT Opcode, IValueT Dd, IValueT Sm);
 
+  // Pattern 111100000D00nnnnddddttttssaammmm | Opcode where Ddddd=Dd, nnnn=Rn,
+  // mmmmm=Rm, tttt=NumDRegs, ElmtSize in {8, 16, 32, 64) and defines ss, and
+  // aa=Align.
+  void emitVMem1Op(IValueT Opcode, IValueT Dd, IValueT Rn, IValueT Rm,
+                   DRegListSize NumDRegs, size_t ElmtSize, IValueT Align,
+                   const char *InstName);
+
   // Pattern cccc011100x1dddd1111mmmm0001nnn where cccc=Cond,
   // x=Opcode, dddd=Rd, nnnn=Rn, mmmm=Rm.
   void emitDivOp(CondARM32::Cond Cond, IValueT Opcode, IValueT Rd, IValueT Rn,
                  IValueT Rm);
 
   // Pattern ccccxxxxxxxfnnnnddddssss1001mmmm where cccc=Cond, dddd=Rd, nnnn=Rn,
   // mmmm=Rm, ssss=Rs, f=SetFlags and xxxxxxx=Opcode.
   void emitMulOp(CondARM32::Cond Cond, IValueT Opcode, IValueT Rd, IValueT Rn,
                  IValueT Rm, IValueT Rs, bool SetFlags);
 
@@ skipping 56 matching lines @@
 
   void emitVFPsss(CondARM32::Cond Cond, IValueT Opcode, const Operand *OpSd,
                   const Operand *OpSn, const Operand *OpSm,
                   const char *InstName);
 };
 
 } // end of namespace ARM32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H