Fix vector load/stores in the ARM assembler.

src/IceInstARM32.cpp

 //===- subzero/src/IceInstARM32.cpp - ARM32 instruction implementation ----===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 47 matching lines @@
   CondARM32::Cond Opposite;
   const char *EmitString;
 } InstARM32CondAttributes[] = {
 #define X(tag, encode, opp, emit)                                              \
   { CondARM32::opp, emit }                                                     \
   ,
     ICEINSTARM32COND_TABLE
 #undef X
 };
 
+size_t getVecElmtBitsize(Type Ty) {
+  return typeWidthInBytes(typeElementType(Ty)) * CHAR_BIT;
+}
+
 } // end of anonymous namespace
 
 const char *InstARM32::getWidthString(Type Ty) {
   return TypeARM32Attributes[Ty].WidthString;
 }
 
 const char *InstARM32::getVecWidthString(Type Ty) {
   return TypeARM32Attributes[Ty].VecWidthString;
 }
 
@@ skipping 1478 matching lines @@
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 1);
   assert(getDest()->hasReg());
   Variable *Dest = getDest();
   Type Ty = Dest->getType();
   const bool IsVector = isVectorType(Ty);
   const bool IsScalarFloat = isScalarFloatingType(Ty);
   const char *ActualOpcode =
       IsVector ? "vld1" : (IsScalarFloat ? "vldr" : "ldr");
-  const char *VectorMarker = IsVector ? ".64" : "";
   const char *WidthString = IsVector ? "" : getWidthString(Ty);
   Str << "\t" << ActualOpcode;
   const bool IsVInst = IsVector || IsScalarFloat;
   if (IsVInst) {
     Str << getPredicate() << WidthString;
   } else {
     Str << WidthString << getPredicate();
   }
-  Str << VectorMarker << "\t";
+  if (IsVector)
+    Str << "." << getVecElmtBitsize(Ty);
+  Str << "\t";
   getDest()->emit(Func);
   Str << ", ";
   getSrc(0)->emit(Func);
 }
 
 template <> void InstARM32Ldr::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 1);
+  auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
   Variable *Dest = getDest();
   const Type DestTy = Dest->getType();
-  auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
-  if (isScalarFloatingType(DestTy)) {
-    switch (DestTy) {
-    default:
-      // TODO(kschimpf) Does this happen?
-      Asm->setNeedsTextFixup();
-      break;
-    case IceType_f32:
-      Asm->vldrs(Dest, getSrc(0), getPredicate(), Func->getTarget());
-      break;
-    case IceType_f64:
-      Asm->vldrd(Dest, getSrc(0), getPredicate(), Func->getTarget());
-      break;
-    }
-  } else if (isVectorType(DestTy))
-    // TODO(kschimpf) Handle case.
-    Asm->setNeedsTextFixup();
-  else
+  switch (DestTy) {
+  default:
+    llvm::report_fatal_error("Ldr on unknown type: " + typeIceString(DestTy));
+  case IceType_i1:
+  case IceType_i8:
+  case IceType_i16:
+  case IceType_i32:
+  case IceType_i64:
     Asm->ldr(Dest, getSrc(0), getPredicate(), Func->getTarget());
-  if (Asm->needsTextFixup())
-    emitUsingTextFixup(Func);
+    break;
+  case IceType_f32:
+    Asm->vldrs(Dest, getSrc(0), getPredicate(), Func->getTarget());
+    break;
+  case IceType_f64:
+    Asm->vldrd(Dest, getSrc(0), getPredicate(), Func->getTarget());
+    break;
+  case IceType_v16i8:
+  case IceType_v8i16:
+  case IceType_v4i32:
+  case IceType_v4f32:
+    Asm->vld1qr(getVecElmtBitsize(DestTy), Dest, getSrc(0), Func->getTarget());
+    break;
+  }
 }
 
 template <> void InstARM32Ldrex::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 1);
   assert(getDest()->hasReg());
   Variable *Dest = getDest();
   Type DestTy = Dest->getType();
@@ skipping 275 matching lines @@
 void InstARM32Str::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 2);
   Type Ty = getSrc(0)->getType();
   const bool IsVectorStore = isVectorType(Ty);
   const bool IsScalarFloat = isScalarFloatingType(Ty);
   const char *Opcode =
       IsVectorStore ? "vst1" : (IsScalarFloat ? "vstr" : "str");
-  const char *VecEltWidthString = IsVectorStore ? ".64" : "";
   Str << "\t" << Opcode;
   const bool IsVInst = IsVectorStore || IsScalarFloat;
   if (IsVInst) {
     Str << getPredicate() << getWidthString(Ty);
   } else {
     Str << getWidthString(Ty) << getPredicate();
   }
-  Str << VecEltWidthString << "\t";
+  if (IsVectorStore)
+    Str << "." << getVecElmtBitsize(Ty);
+  Str << "\t";
   getSrc(0)->emit(Func);
   Str << ", ";
   getSrc(1)->emit(Func);
 }
 
 void InstARM32Str::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 2);
-  Type Ty = getSrc(0)->getType();
   auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
-  if (isScalarFloatingType(Ty)) {
-    switch (Ty) {
-    default:
-      // TODO(kschimpf) Does this happen?
-      Asm->setNeedsTextFixup();
-      break;
-    case IceType_f32:
-      Asm->vstrs(getSrc(0), getSrc(1), getPredicate(), Func->getTarget());
-      break;
-    case IceType_f64:
-      Asm->vstrd(getSrc(0), getSrc(1), getPredicate(), Func->getTarget());
-      break;
-    }
-  } else if (isVectorType(Ty))
-    // TODO(kschimpf) Handle case.
-    Asm->setNeedsTextFixup();
-  else
-    Asm->str(getSrc(0), getSrc(1), getPredicate(), Func->getTarget());
-  if (Asm->needsTextFixup())
-    emitUsingTextFixup(Func);
+  const Operand *Src0 = getSrc(0);

[Jim Stichnoth, 2016/02/04 20:47:37]

Maybe also "const Operand *Src1 = getSrc(1);" for symmetry below.

[Karl, 2016/02/04 21:55:22]

Done.

+  Type Ty = Src0->getType();
+  switch (Ty) {
+  default:
+    llvm::report_fatal_error("Str on unknown type: " + typeIceString(Ty));
+  case IceType_i1:
+  case IceType_i8:
+  case IceType_i16:
+  case IceType_i32:
+  case IceType_i64:
+    Asm->str(Src0, getSrc(1), getPredicate(), Func->getTarget());
+    break;
+  case IceType_f32:
+    Asm->vstrs(Src0, getSrc(1), getPredicate(), Func->getTarget());
+    break;
+  case IceType_f64:
+    Asm->vstrd(Src0, getSrc(1), getPredicate(), Func->getTarget());
+    break;
+  case IceType_v16i8:
+  case IceType_v8i16:
+  case IceType_v4i32:
+  case IceType_v4f32:
+    Asm->vst1qr(getVecElmtBitsize(Ty), Src0, getSrc(1), Func->getTarget());
+    break;
+  }
 }
 
 void InstARM32Str::dump(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrDump();
   Type Ty = getSrc(0)->getType();
   dumpOpcodePred(Str, "str", Ty);
   Str << " ";
   getSrc(1)->dump(Func);
@@ skipping 584 matching lines @@
 
 template class InstARM32FourAddrGPR<InstARM32::Mla>;
 template class InstARM32FourAddrGPR<InstARM32::Mls>;
 
 template class InstARM32CmpLike<InstARM32::Cmn>;
 template class InstARM32CmpLike<InstARM32::Cmp>;
 template class InstARM32CmpLike<InstARM32::Tst>;
 
 } // end of namespace ARM32
 } // end of namespace Ice