Add VORR instruction to the integrated ARM assembler.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 2173 matching lines @@
   // cccc11100D11nnnndddd101sN0M0mmmm where cccc=Cond, s=1, Ddddd=Rd, Nnnnn=Rn,
   // and Mmmmm=Rm.
   constexpr const char *Vaddd = "vaddd";
   constexpr IValueT VadddOpcode = B21 | B20;
   emitVFPddd(Cond, VadddOpcode, OpDd, OpDn, OpDm, Vaddd);
 }
 
 void AssemblerARM32::vandq(const Operand *OpQd, const Operand *OpQm,
                            const Operand *OpQn) {
   // VAND (register) - ARM section A8.8.287, encoding A1:
-  //   vand.<dt> <Qd>, <Qn>, <Qm>
+  //   vand <Qd>, <Qn>, <Qm>
   //
   // 111100100D00nnn0ddd00001N1M1mmm0 where Dddd=OpQd, Nnnn=OpQm, and Mmmm=OpQm.
-  constexpr const char *Vandqi = "vandqi";
-  constexpr IValueT VandqiOpcode = B8 | B4;
+  constexpr const char *Vandq = "vandq";
+  constexpr IValueT VandqOpcode = B8 | B4;
   constexpr Type ElmtTy = IceType_i8;
-  emitSIMDqqq(VandqiOpcode, ElmtTy, OpQd, OpQm, OpQn, Vandqi);
+  emitSIMDqqq(VandqOpcode, ElmtTy, OpQd, OpQm, OpQn, Vandq);
 }
 
 void AssemblerARM32::vcmpd(const Operand *OpDd, const Operand *OpDm,
                            CondARM32::Cond Cond) {
   constexpr const char *Vcmpd = "vcmpd";
   IValueT Dd = encodeDRegister(OpDd, "Dd", Vcmpd);
   IValueT Dm = encodeDRegister(OpDm, "Dm", Vcmpd);
   constexpr IValueT VcmpdOpcode = B23 | B21 | B20 | B18 | B6;
   constexpr IValueT Dn = 0;
   emitVFPddd(Cond, VcmpdOpcode, Dd, Dn, Dm);
@@ skipping 504 matching lines @@
   // VMUL (floating-point) - ARM section A8.8.351, encoding A2:
   //   vmul<c>.f64 <Dd>, <Dn>, <Dm>
   //
   // cccc11100D10nnnndddd101sN0M0mmmm where cccc=Cond, s=1, Ddddd=Rd, Nnnnn=Rn,
   // and Mmmmm=Rm.
   constexpr const char *Vmuld = "vmuld";
   constexpr IValueT VmuldOpcode = B21;
   emitVFPddd(Cond, VmuldOpcode, OpDd, OpDn, OpDm, Vmuld);
 }
 
+void AssemblerARM32::vorrq(const Operand *OpQd, const Operand *OpQm,
+                           const Operand *OpQn) {
+  // VORR (register) - ARM section A8.8.360, encoding A1:
+  //   vorr <Qd>, <Qn>, <Qm>
+  //
+  // 111100100D10nnn0ddd00001N1M1mmm0 where Dddd=OpQd, Nnnn=OpQm, and Mmmm=OpQm.
+  constexpr const char *Vorrq = "vandq";

[Jim Stichnoth, 2016/02/02 21:47:13]

vorrq

[Karl, 2016/02/02 21:52:45]

Done.

+  constexpr IValueT VorrqOpcode = B21 | B8 | B4;
+  constexpr Type ElmtTy = IceType_i8;
+  emitSIMDqqq(VorrqOpcode, ElmtTy, OpQd, OpQm, OpQn, Vorrq);
+}
+
 void AssemblerARM32::vstrd(const Operand *OpDd, const Operand *OpAddress,
                            CondARM32::Cond Cond, const TargetInfo &TInfo) {
   // VSTR - ARM section A8.8.413, encoding A1:
   //   vstr<c> <Dd>, [<Rn>{, #+/-<Imm>}]
   //
   // cccc1101UD00nnnndddd1011iiiiiiii where cccc=Cond, nnnn=Rn, Ddddd=Rd,
   // iiiiiiii=abs(Imm >> 2), and U=1 if Imm>=0.
   constexpr const char *Vstrd = "vstrd";
   IValueT Dd = encodeDRegister(OpDd, "Dd", Vstrd);
   assert(CondARM32::isDefined(Cond));
@@ skipping 146 matching lines @@
   constexpr const char *Vsqrts = "vsqrts";
   IValueT Sd = encodeSRegister(OpSd, "Sd", Vsqrts);
   IValueT Sm = encodeSRegister(OpSm, "Sm", Vsqrts);
   constexpr IValueT VsqrtsOpcode = B23 | B21 | B20 | B16 | B7 | B6;
   constexpr IValueT S0 = 0;
   emitVFPsss(Cond, VsqrtsOpcode, Sd, S0, Sm);
 }
 
 } // end of namespace ARM32
 } // end of namespace Ice