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Issue 1659883002: Reland of MIPS: Add FPXX support to MIPS32R2 (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Fix failure in RunFloat64InsertLowWord32 test Created 4 years, 10 months ago
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1 // Copyright 2011 the V8 project authors. All rights reserved. 1 // Copyright 2011 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include <limits.h> 5 #include <limits.h>
6 #include <stdarg.h> 6 #include <stdarg.h>
7 #include <stdlib.h> 7 #include <stdlib.h>
8 #include <cmath> 8 #include <cmath>
9 9
10 #if V8_TARGET_ARCH_MIPS 10 #if V8_TARGET_ARCH_MIPS
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3399 switch (get_instr()->RsFieldRaw()) { 3399 switch (get_instr()->RsFieldRaw()) {
3400 case CFC1: 3400 case CFC1:
3401 // At the moment only FCSR is supported. 3401 // At the moment only FCSR is supported.
3402 DCHECK(fs_reg() == kFCSRRegister); 3402 DCHECK(fs_reg() == kFCSRRegister);
3403 set_register(rt_reg(), FCSR_); 3403 set_register(rt_reg(), FCSR_);
3404 break; 3404 break;
3405 case MFC1: 3405 case MFC1:
3406 set_register(rt_reg(), get_fpu_register_word(fs_reg())); 3406 set_register(rt_reg(), get_fpu_register_word(fs_reg()));
3407 break; 3407 break;
3408 case MFHC1: 3408 case MFHC1:
3409 set_register(rt_reg(), get_fpu_register_hi_word(fs_reg())); 3409 if (IsFp64Mode()) {
3410 set_register(rt_reg(), get_fpu_register_hi_word(fs_reg()));
3411 } else {
3412 set_register(rt_reg(), get_fpu_register_word(fs_reg() + 1));
3413 }
3410 break; 3414 break;
3411 case CTC1: { 3415 case CTC1: {
3412 // At the moment only FCSR is supported. 3416 // At the moment only FCSR is supported.
3413 DCHECK(fs_reg() == kFCSRRegister); 3417 DCHECK(fs_reg() == kFCSRRegister);
3414 int32_t reg = registers_[rt_reg()]; 3418 int32_t reg = registers_[rt_reg()];
3415 if (IsMipsArchVariant(kMips32r6)) { 3419 if (IsMipsArchVariant(kMips32r6)) {
3416 FCSR_ = reg | kFCSRNaN2008FlagMask; 3420 FCSR_ = reg | kFCSRNaN2008FlagMask;
3417 } else { 3421 } else {
3418 DCHECK(IsMipsArchVariant(kMips32r1) || IsMipsArchVariant(kMips32r2)); 3422 DCHECK(IsMipsArchVariant(kMips32r1) || IsMipsArchVariant(kMips32r2));
3419 FCSR_ = reg & ~kFCSRNaN2008FlagMask; 3423 FCSR_ = reg & ~kFCSRNaN2008FlagMask;
3420 } 3424 }
3421 break; 3425 break;
3422 } 3426 }
3423 case MTC1: 3427 case MTC1:
3424 // Hardware writes upper 32-bits to zero on mtc1. 3428 // Hardware writes upper 32-bits to zero on mtc1.
3425 set_fpu_register_hi_word(fs_reg(), 0); 3429 set_fpu_register_hi_word(fs_reg(), 0);
3426 set_fpu_register_word(fs_reg(), registers_[rt_reg()]); 3430 set_fpu_register_word(fs_reg(), registers_[rt_reg()]);
3427 break; 3431 break;
3428 case MTHC1: 3432 case MTHC1:
3429 set_fpu_register_hi_word(fs_reg(), registers_[rt_reg()]); 3433 if (IsFp64Mode()) {
3434 set_fpu_register_hi_word(fs_reg(), registers_[rt_reg()]);
3435 } else {
3436 set_fpu_register_word(fs_reg() + 1, registers_[rt_reg()]);
3437 }
3430 break; 3438 break;
3431 case S: { 3439 case S: {
3432 DecodeTypeRegisterSRsType(); 3440 DecodeTypeRegisterSRsType();
3433 break; 3441 break;
3434 } 3442 }
3435 case D: 3443 case D:
3436 DecodeTypeRegisterDRsType(); 3444 DecodeTypeRegisterDRsType();
3437 break; 3445 break;
3438 case W: 3446 case W:
3439 DecodeTypeRegisterWRsType(); 3447 DecodeTypeRegisterWRsType();
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4615 4623
4616 4624
4617 #undef UNSUPPORTED 4625 #undef UNSUPPORTED
4618 4626
4619 } // namespace internal 4627 } // namespace internal
4620 } // namespace v8 4628 } // namespace v8
4621 4629
4622 #endif // USE_SIMULATOR 4630 #endif // USE_SIMULATOR
4623 4631
4624 #endif // V8_TARGET_ARCH_MIPS 4632 #endif // V8_TARGET_ARCH_MIPS
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