Rename fletch -> dartino

src/vm/interpreter_arm.cc

 // Copyright (c) 2015, the Dartino project authors. Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE.md file.
 
-#if defined(FLETCH_TARGET_ARM)
+#if defined(DARTINO_TARGET_ARM)
 
 #include "src/shared/bytecodes.h"
 #include "src/shared/names.h"
 #include "src/shared/selectors.h"
 
 #include "src/vm/assembler.h"
 #include "src/vm/generator.h"
 #include "src/vm/interpreter.h"
 #include "src/vm/intrinsics.h"
 #include "src/vm/object.h"
 #include "src/vm/process.h"
 #include "src/vm/program.h"
 
 #define __ assembler()->
 
-namespace fletch {
+namespace dartino {
 
 class InterpreterGenerator {
  public:
   explicit InterpreterGenerator(Assembler* assembler) : assembler_(assembler) {}
 
   void Generate();
 
   virtual void GeneratePrologue() = 0;
   virtual void GenerateEpilogue() = 0;
 
@@ skipping 392 matching lines @@
   Push(R2);
   __ add(R5, R0, Immediate(Function::kSize - HeapObject::kTag));
   CheckStackOverflow(0);
   Dispatch(0);
 }
 
 void InterpreterGeneratorARM::GenerateBytecodePrologue(const char* name) {
   __ SwitchToText();
   __ AlignToPowerOfTwo(3);
   __ nop();
-#ifdef FLETCH_THUMB_ONLY
+#ifdef DARTINO_THUMB_ONLY
   // Thumb is has 16-bit nop's, not 32-bit.
   __ nop();
 #endif
   __ Bind("Debug_", name);
   __ bl("DebugAtBytecode");
   __ AlignToPowerOfTwo(3);
   __ Bind("", name);
 }
 
 void InterpreterGeneratorARM::GenerateDebugAtBytecode() {
@@ skipping 954 matching lines @@
 void InterpreterGeneratorARM::DoIntrinsicListLength() {
   // Load the backing store (array) from the first instance field of the list.
   LoadLocal(R2, 0);  // List.
   __ ldr(R2, Address(R2, Instance::kSize - HeapObject::kTag));
   __ ldr(R0, Address(R2, Array::kLengthOffset - HeapObject::kTag));
 
   __ mov(PC, LR);
 }
 
 void InterpreterGeneratorARM::Push(Register reg) {
-#ifdef FLETCH_THUMB_ONLY
+#ifdef DARTINO_THUMB_ONLY
   StoreLocal(reg, -1);
   __ sub(R6, R6, Immediate(1 * kWordSize));
 #else
   __ str(reg, Address(R6, -1 * kWordSize), WRITE_BACK);
 #endif
 }
 
 void InterpreterGeneratorARM::Pop(Register reg) {
-#ifdef FLETCH_THUMB_ONLY
+#ifdef DARTINO_THUMB_ONLY
   LoadLocal(reg, 0);
   Drop(1);
 #else
   __ ldr(reg, R6, Immediate(kWordSize));
 #endif
 }
 
 void InterpreterGeneratorARM::Return(bool is_return_null) {
   // Materialize the result in register R0.
   if (is_return_null) {
@@ skipping 21 matching lines @@
 
 void InterpreterGeneratorARM::Drop(int n) {
   __ add(R6, R6, Immediate(n * kWordSize));
 }
 
 void InterpreterGeneratorARM::Drop(Register reg) {
   __ add(R6, R6, Operand(reg, TIMES_WORD_SIZE));
 }
 
 void InterpreterGeneratorARM::DropNAndSetTop(int dropping_slots, Register reg) {
-#ifdef FLETCH_THUMB_ONLY
+#ifdef DARTINO_THUMB_ONLY
   Drop(dropping_slots);
   StoreLocal(reg, 0);
 #else
   __ str(reg, Address(R6, dropping_slots * kWordSize), WRITE_BACK);
 #endif
 }
 
 void InterpreterGeneratorARM::LoadFramePointer(Register reg) {
   __ ldr(reg, Address(SP, spill_size_));
 }
@@ skipping 449 matching lines @@
   // Compute the address of the first and last instance field.
   __ sub(R7, R0, Immediate(kWordSize + HeapObject::kTag));
   __ add(R7, R7, R2);
   __ add(R9, R0, Immediate(Instance::kSize - HeapObject::kTag));
 
   Label loop, done;
   __ Bind(&loop);
   __ cmp(R9, R7);
   __ b(HI, &done);
   Pop(R1);
-#ifdef FLETCH_THUMB_ONLY
+#ifdef DARTINO_THUMB_ONLY
   __ str(R1, Address(R7, 0));
   __ sub(R7, R7, Immediate(1 * kWordSize));
 #else
   __ str(R1, R7, Immediate(-1 * kWordSize));
 #endif
   __ b(&loop);
 
   __ Bind(&done);
   Push(R0);
   Dispatch(kAllocateLength);
@@ skipping 46 matching lines @@
     Label done;
     __ b(HI, &done);
     __ mov(R0, Immediate(size));
     __ b(&check_stack_overflow_);
     __ Bind(&done);
   }
 }
 
 void InterpreterGeneratorARM::Dispatch(int size) {
 // Load the next bytecode through R5 and dispatch to it.
-#ifdef FLETCH_THUMB_ONLY
+#ifdef DARTINO_THUMB_ONLY
   __ ldrb(R7, Address(R5, size));
   if (size > 0) {
     __ add(R5, R5, Immediate(size));
   }
 #else
   __ ldrb(R7, Address(R5, size), WRITE_BACK);
 #endif
   __ ldr(R9, "Interpret_DispatchTable");
   __ ldr(PC, Address(R9, Operand(R7, TIMES_WORD_SIZE)));
   __ GenerateConstantPool();
@@ skipping 39 matching lines @@
   StoreFramePointer(R5);
 
   // Set the bytecode pointer from the stack.
   __ ldr(R5, Address(R5, -kWordSize));
 
   // Pop and branch to resume address.
   Pop(LR);
   __ mov(PC, LR);
 }
 
-}  // namespace fletch
+}  // namespace dartino
 
-#endif  // defined(FLETCH_TARGET_ARM)
+#endif  // defined(DARTINO_TARGET_ARM)