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| 1 /** | |
| 2 ****************************************************************************** | |
| 3 * @file Template/system_stm32f7xx.c | |
| 4 * @author MCD Application Team | |
| 5 * @version V1.1.1 | |
| 6 * @date 18-November-2015 | |
| 7 * @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File. | |
| 8 * | |
| 9 * This file provides two functions and one global variable to be called from
| |
| 10 * user application: | |
| 11 * - SystemInit(): This function is called at startup just after reset and
| |
| 12 * before branch to main program. This call is made inside | |
| 13 * the "startup_stm32f7xx.s" file. | |
| 14 * | |
| 15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be u
sed | |
| 16 * by the user application to setup the SysTic
k | |
| 17 * timer or configure other parameters. | |
| 18 * | |
| 19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and mus
t | |
| 20 * be called whenever the core clock is changed | |
| 21 * during program execution. | |
| 22 * | |
| 23 * | |
| 24 ****************************************************************************** | |
| 25 * @attention | |
| 26 * | |
| 27 * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> | |
| 28 * | |
| 29 * Redistribution and use in source and binary forms, with or without modificat
ion, | |
| 30 * are permitted provided that the following conditions are met: | |
| 31 * 1. Redistributions of source code must retain the above copyright notice, | |
| 32 * this list of conditions and the following disclaimer. | |
| 33 * 2. Redistributions in binary form must reproduce the above copyright notic
e, | |
| 34 * this list of conditions and the following disclaimer in the documentati
on | |
| 35 * and/or other materials provided with the distribution. | |
| 36 * 3. Neither the name of STMicroelectronics nor the names of its contributor
s | |
| 37 * may be used to endorse or promote products derived from this software | |
| 38 * without specific prior written permission. | |
| 39 * | |
| 40 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
| 41 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
| 42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE A
RE | |
| 43 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE | |
| 44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
| 45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR | |
| 46 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER | |
| 47 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY
, | |
| 48 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE US
E | |
| 49 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
| 50 * | |
| 51 ****************************************************************************** | |
| 52 */ | |
| 53 | |
| 54 /** @addtogroup CMSIS | |
| 55 * @{ | |
| 56 */ | |
| 57 | |
| 58 /** @addtogroup stm32f7xx_system | |
| 59 * @{ | |
| 60 */ | |
| 61 | |
| 62 /** @addtogroup STM32F7xx_System_Private_Includes | |
| 63 * @{ | |
| 64 */ | |
| 65 | |
| 66 #include "stm32f7xx.h" | |
| 67 | |
| 68 #if !defined (HSE_VALUE) | |
| 69 #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External o
scillator in Hz */ | |
| 70 #endif /* HSE_VALUE */ | |
| 71 | |
| 72 #if !defined (HSI_VALUE) | |
| 73 #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillato
r in Hz*/ | |
| 74 #endif /* HSI_VALUE */ | |
| 75 | |
| 76 /** | |
| 77 * @} | |
| 78 */ | |
| 79 | |
| 80 /** @addtogroup STM32F7xx_System_Private_TypesDefinitions | |
| 81 * @{ | |
| 82 */ | |
| 83 | |
| 84 /** | |
| 85 * @} | |
| 86 */ | |
| 87 | |
| 88 /** @addtogroup STM32F7xx_System_Private_Defines | |
| 89 * @{ | |
| 90 */ | |
| 91 | |
| 92 /************************* Miscellaneous Configuration ************************/ | |
| 93 /*!< Uncomment the following line if you need to use external SDRAM mounted | |
| 94 on DK as data memory */ | |
| 95 // Always undefine this as SDRAM is initialized later. | |
| 96 #undef DATA_IN_ExtSDRAM | |
| 97 | |
| 98 /*!< Uncomment the following line if you need to relocate your vector Table in | |
| 99 Internal SRAM. */ | |
| 100 /* #define VECT_TAB_SRAM */ | |
| 101 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. | |
| 102 This value must be a multiple of 0x200. */ | |
| 103 /******************************************************************************/ | |
| 104 | |
| 105 /** | |
| 106 * @} | |
| 107 */ | |
| 108 | |
| 109 /** @addtogroup STM32F7xx_System_Private_Macros | |
| 110 * @{ | |
| 111 */ | |
| 112 | |
| 113 /** | |
| 114 * @} | |
| 115 */ | |
| 116 | |
| 117 /** @addtogroup STM32F7xx_System_Private_Variables | |
| 118 * @{ | |
| 119 */ | |
| 120 | |
| 121 /* This variable is updated in three ways: | |
| 122 1) by calling CMSIS function SystemCoreClockUpdate() | |
| 123 2) by calling HAL API function HAL_RCC_GetHCLKFreq() | |
| 124 3) each time HAL_RCC_ClockConfig() is called to configure the system clock
frequency | |
| 125 Note: If you use this function to configure the system clock; then ther
e | |
| 126 is no need to call the 2 first functions listed above, since Syst
emCoreClock | |
| 127 variable is updated automatically. | |
| 128 */ | |
| 129 uint32_t SystemCoreClock = 16000000; | |
| 130 __IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6,
7, 8, 9}; | |
| 131 | |
| 132 /** | |
| 133 * @} | |
| 134 */ | |
| 135 | |
| 136 /** @addtogroup STM32F7xx_System_Private_FunctionPrototypes | |
| 137 * @{ | |
| 138 */ | |
| 139 #if defined (DATA_IN_ExtSDRAM) | |
| 140 static void SystemInit_ExtMemCtl(void); | |
| 141 #endif /* DATA_IN_ExtSDRAM */ | |
| 142 | |
| 143 /** | |
| 144 * @} | |
| 145 */ | |
| 146 | |
| 147 /** @addtogroup STM32F7xx_System_Private_Functions | |
| 148 * @{ | |
| 149 */ | |
| 150 | |
| 151 /** | |
| 152 * @brief Setup the microcontroller system | |
| 153 * Initialize the Embedded Flash Interface, the PLL and update the | |
| 154 * SystemFrequency variable. | |
| 155 * @param None | |
| 156 * @retval None | |
| 157 */ | |
| 158 void SystemInit(void) | |
| 159 { | |
| 160 /* FPU settings ------------------------------------------------------------*/ | |
| 161 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) | |
| 162 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Acce
ss */ | |
| 163 #endif | |
| 164 /* Reset the RCC clock configuration to the default reset state ------------*/ | |
| 165 /* Set HSION bit */ | |
| 166 RCC->CR |= (uint32_t)0x00000001; | |
| 167 | |
| 168 /* Reset CFGR register */ | |
| 169 RCC->CFGR = 0x00000000; | |
| 170 | |
| 171 /* Reset HSEON, CSSON and PLLON bits */ | |
| 172 RCC->CR &= (uint32_t)0xFEF6FFFF; | |
| 173 | |
| 174 /* Reset PLLCFGR register */ | |
| 175 RCC->PLLCFGR = 0x24003010; | |
| 176 | |
| 177 /* Reset HSEBYP bit */ | |
| 178 RCC->CR &= (uint32_t)0xFFFBFFFF; | |
| 179 | |
| 180 /* Disable all interrupts */ | |
| 181 RCC->CIR = 0x00000000; | |
| 182 | |
| 183 #if defined (DATA_IN_ExtSDRAM) | |
| 184 SystemInit_ExtMemCtl(); | |
| 185 #endif /* DATA_IN_ExtSDRAM */ | |
| 186 | |
| 187 /* Configure the Vector Table location add offset address ------------------*/ | |
| 188 #ifdef VECT_TAB_SRAM | |
| 189 SCB->VTOR = SRAM1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Intern
al SRAM */ | |
| 190 #else | |
| 191 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Intern
al FLASH */ | |
| 192 #endif | |
| 193 } | |
| 194 | |
| 195 /** | |
| 196 * @brief Update SystemCoreClock variable according to Clock Register Values. | |
| 197 * The SystemCoreClock variable contains the core clock (HCLK), it can | |
| 198 * be used by the user application to setup the SysTick timer or config
ure | |
| 199 * other parameters. | |
| 200 * | |
| 201 * @note Each time the core clock (HCLK) changes, this function must be calle
d | |
| 202 * to update SystemCoreClock variable value. Otherwise, any configurati
on | |
| 203 * based on this variable will be incorrect. | |
| 204 * | |
| 205 * @note - The system frequency computed by this function is not the real | |
| 206 * frequency in the chip. It is calculated based on the predefined | |
| 207 * constant and the selected clock source: | |
| 208 * | |
| 209 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VA
LUE(*) | |
| 210 * | |
| 211 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VA
LUE(**) | |
| 212 * | |
| 213 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VA
LUE(**) | |
| 214 * or HSI_VALUE(*) multiplied/divided by the PLL factors. | |
| 215 * | |
| 216 * (*) HSI_VALUE is a constant defined in stm32f7xx.h file (default val
ue | |
| 217 * 16 MHz) but the real value may vary depending on the variations | |
| 218 * in voltage and temperature. | |
| 219 * | |
| 220 * (**) HSE_VALUE is a constant defined in stm32f7xx.h file (default va
lue | |
| 221 * 25 MHz), user has to ensure that HSE_VALUE is same as the real | |
| 222 * frequency of the crystal used. Otherwise, this function may | |
| 223 * have wrong result. | |
| 224 * | |
| 225 * - The result of this function could be not correct when using fracti
onal | |
| 226 * value for HSE crystal. | |
| 227 * | |
| 228 * @param None | |
| 229 * @retval None | |
| 230 */ | |
| 231 void SystemCoreClockUpdate(void) | |
| 232 { | |
| 233 uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; | |
| 234 | |
| 235 /* Get SYSCLK source -------------------------------------------------------*/ | |
| 236 tmp = RCC->CFGR & RCC_CFGR_SWS; | |
| 237 | |
| 238 switch (tmp) | |
| 239 { | |
| 240 case 0x00: /* HSI used as system clock source */ | |
| 241 SystemCoreClock = HSI_VALUE; | |
| 242 break; | |
| 243 case 0x04: /* HSE used as system clock source */ | |
| 244 SystemCoreClock = HSE_VALUE; | |
| 245 break; | |
| 246 case 0x08: /* PLL used as system clock source */ | |
| 247 | |
| 248 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N | |
| 249 SYSCLK = PLL_VCO / PLL_P | |
| 250 */ | |
| 251 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; | |
| 252 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; | |
| 253 | |
| 254 if (pllsource != 0) | |
| 255 { | |
| 256 /* HSE used as PLL clock source */ | |
| 257 pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); | |
| 258 } | |
| 259 else | |
| 260 { | |
| 261 /* HSI used as PLL clock source */ | |
| 262 pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
| |
| 263 } | |
| 264 | |
| 265 pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; | |
| 266 SystemCoreClock = pllvco/pllp; | |
| 267 break; | |
| 268 default: | |
| 269 SystemCoreClock = HSI_VALUE; | |
| 270 break; | |
| 271 } | |
| 272 /* Compute HCLK frequency --------------------------------------------------*/ | |
| 273 /* Get HCLK prescaler */ | |
| 274 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; | |
| 275 /* HCLK frequency */ | |
| 276 SystemCoreClock >>= tmp; | |
| 277 } | |
| 278 | |
| 279 #if defined (DATA_IN_ExtSDRAM) | |
| 280 /** | |
| 281 * @brief Setup the external memory controller. | |
| 282 * Called in startup_stm32f7xx.s before jump to main. | |
| 283 * This function configures the external memories (SDRAM) | |
| 284 * This SDRAM will be used as program data memory (including heap and s
tack). | |
| 285 * @param None | |
| 286 * @retval None | |
| 287 */ | |
| 288 void SystemInit_ExtMemCtl(void) | |
| 289 { | |
| 290 #error "SystemInit_ExtMemCtl should not be used!" | |
| 291 register uint32_t tmpreg = 0, timeout = 0xFFFF; | |
| 292 register __IO uint32_t index; | |
| 293 | |
| 294 /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG and GPIOH interface | |
| 295 clock */ | |
| 296 RCC->AHB1ENR |= 0x000000FC; | |
| 297 | |
| 298 /* Connect PCx pins to FMC Alternate function */ | |
| 299 GPIOC->AFR[0] = 0x0000C000; | |
| 300 GPIOC->AFR[1] = 0x00000000; | |
| 301 /* Configure PCx pins in Alternate function mode */ | |
| 302 GPIOC->MODER = 0x00000080; | |
| 303 /* Configure PCx pins speed to 50 MHz */ | |
| 304 GPIOC->OSPEEDR = 0x00000080; | |
| 305 /* Configure PCx pins Output type to push-pull */ | |
| 306 GPIOC->OTYPER = 0x00000000; | |
| 307 /* No pull-up, pull-down for PCx pins */ | |
| 308 GPIOC->PUPDR = 0x00000040; | |
| 309 | |
| 310 /* Connect PDx pins to FMC Alternate function */ | |
| 311 GPIOD->AFR[0] = 0x0000C0CC; | |
| 312 GPIOD->AFR[1] = 0xCC000CCC; | |
| 313 /* Configure PDx pins in Alternate function mode */ | |
| 314 GPIOD->MODER = 0xA02A008A; | |
| 315 /* Configure PDx pins speed to 50 MHz */ | |
| 316 GPIOD->OSPEEDR = 0xA02A008A; | |
| 317 /* Configure PDx pins Output type to push-pull */ | |
| 318 GPIOD->OTYPER = 0x00000000; | |
| 319 /* No pull-up, pull-down for PDx pins */ | |
| 320 GPIOD->PUPDR = 0x50150045; | |
| 321 | |
| 322 /* Connect PEx pins to FMC Alternate function */ | |
| 323 GPIOE->AFR[0] = 0xC00000CC; | |
| 324 GPIOE->AFR[1] = 0xCCCCCCCC; | |
| 325 /* Configure PEx pins in Alternate function mode */ | |
| 326 GPIOE->MODER = 0xAAAA800A; | |
| 327 /* Configure PEx pins speed to 50 MHz */ | |
| 328 GPIOE->OSPEEDR = 0xAAAA800A; | |
| 329 /* Configure PEx pins Output type to push-pull */ | |
| 330 GPIOE->OTYPER = 0x00000000; | |
| 331 /* No pull-up, pull-down for PEx pins */ | |
| 332 GPIOE->PUPDR = 0x55554005; | |
| 333 | |
| 334 /* Connect PFx pins to FMC Alternate function */ | |
| 335 GPIOF->AFR[0] = 0x00CCCCCC; | |
| 336 GPIOF->AFR[1] = 0xCCCCC000; | |
| 337 /* Configure PFx pins in Alternate function mode */ | |
| 338 GPIOF->MODER = 0xAA800AAA; | |
| 339 /* Configure PFx pins speed to 50 MHz */ | |
| 340 GPIOF->OSPEEDR = 0xAA800AAA; | |
| 341 /* Configure PFx pins Output type to push-pull */ | |
| 342 GPIOF->OTYPER = 0x00000000; | |
| 343 /* No pull-up, pull-down for PFx pins */ | |
| 344 GPIOF->PUPDR = 0x55400555; | |
| 345 | |
| 346 /* Connect PGx pins to FMC Alternate function */ | |
| 347 GPIOG->AFR[0] = 0x00CC00CC; | |
| 348 GPIOG->AFR[1] = 0xC000000C; | |
| 349 /* Configure PGx pins in Alternate function mode */ | |
| 350 GPIOG->MODER = 0x80020A0A; | |
| 351 /* Configure PGx pins speed to 50 MHz */ | |
| 352 GPIOG->OSPEEDR = 0x80020A0A; | |
| 353 /* Configure PGx pins Output type to push-pull */ | |
| 354 GPIOG->OTYPER = 0x00000000; | |
| 355 /* No pull-up, pull-down for PGx pins */ | |
| 356 GPIOG->PUPDR = 0x40010505; | |
| 357 | |
| 358 /* Connect PHx pins to FMC Alternate function */ | |
| 359 GPIOH->AFR[0] = 0x00C0C000; | |
| 360 GPIOH->AFR[1] = 0x00000000; | |
| 361 /* Configure PHx pins in Alternate function mode */ | |
| 362 GPIOH->MODER = 0x00000880; | |
| 363 /* Configure PHx pins speed to 50 MHz */ | |
| 364 GPIOH->OSPEEDR = 0x00000880; | |
| 365 /* Configure PHx pins Output type to push-pull */ | |
| 366 GPIOH->OTYPER = 0x00000000; | |
| 367 /* No pull-up, pull-down for PHx pins */ | |
| 368 GPIOH->PUPDR = 0x00000440; | |
| 369 | |
| 370 /* Enable the FMC interface clock */ | |
| 371 RCC->AHB3ENR |= 0x00000001; | |
| 372 | |
| 373 /* Configure and enable SDRAM bank1 */ | |
| 374 FMC_Bank5_6->SDCR[0] = 0x00001954; | |
| 375 FMC_Bank5_6->SDTR[0] = 0x01115351; | |
| 376 | |
| 377 /* SDRAM initialization sequence */ | |
| 378 /* Clock enable command */ | |
| 379 FMC_Bank5_6->SDCMR = 0x00000011; | |
| 380 tmpreg = FMC_Bank5_6->SDSR & 0x00000020; | |
| 381 while((tmpreg != 0) && (timeout-- > 0)) | |
| 382 { | |
| 383 tmpreg = FMC_Bank5_6->SDSR & 0x00000020; | |
| 384 } | |
| 385 | |
| 386 /* Delay */ | |
| 387 for (index = 0; index<1000; index++); | |
| 388 | |
| 389 /* PALL command */ | |
| 390 FMC_Bank5_6->SDCMR = 0x00000012; | |
| 391 timeout = 0xFFFF; | |
| 392 while((tmpreg != 0) && (timeout-- > 0)) | |
| 393 { | |
| 394 tmpreg = FMC_Bank5_6->SDSR & 0x00000020; | |
| 395 } | |
| 396 | |
| 397 /* Auto refresh command */ | |
| 398 FMC_Bank5_6->SDCMR = 0x000000F3; | |
| 399 timeout = 0xFFFF; | |
| 400 while((tmpreg != 0) && (timeout-- > 0)) | |
| 401 { | |
| 402 tmpreg = FMC_Bank5_6->SDSR & 0x00000020; | |
| 403 } | |
| 404 | |
| 405 /* MRD register program */ | |
| 406 FMC_Bank5_6->SDCMR = 0x00044014; | |
| 407 timeout = 0xFFFF; | |
| 408 while((tmpreg != 0) && (timeout-- > 0)) | |
| 409 { | |
| 410 tmpreg = FMC_Bank5_6->SDSR & 0x00000020; | |
| 411 } | |
| 412 | |
| 413 /* Set refresh count */ | |
| 414 tmpreg = FMC_Bank5_6->SDRTR; | |
| 415 FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1)); | |
| 416 | |
| 417 /* Disable write protection */ | |
| 418 tmpreg = FMC_Bank5_6->SDCR[0]; | |
| 419 FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); | |
| 420 } | |
| 421 #endif /* DATA_IN_ExtSDRAM */ | |
| 422 | |
| 423 /** | |
| 424 * @} | |
| 425 */ | |
| 426 | |
| 427 /** | |
| 428 * @} | |
| 429 */ | |
| 430 | |
| 431 /** | |
| 432 * @} | |
| 433 */ | |
| 434 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ | |
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Chromium Code Reviews
Issue 1659163007:
Rename fletch -> dartino (Closed)
Base URL: https://github.com/dartino/sdk.git@master