platforms/stm/disco_fletch/template/startup_stm32f746xx.s - Issue 1659163007: Rename fletch -> dartino

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Issue 1659163007: Rename fletch -> dartino (Closed) Base URL: https://github.com/dartino/sdk.git@master

Patch Set: Created 4 years, 10 months ago

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1 /**

2 ******************************************************************************

3 * @file startup_stm32f746xx.s

4 * @author MCD Application Team

5 * @Version V1.0.2

6 * @Date 21-September-2015

7 * @brief STM32F746xx Devices vector table for GCC based toolchain.

8 * This module performs:

9 * - Set the initial SP

10 * - Set the initial PC == Reset_Handler,

11 * - Set the vector table entries with the exceptions ISR addres s

12 * - Branches to main in the C library (which eventually

13 * calls main()).

14 * After Reset the Cortex-M7 processor is in Thread mode,

15 * priority is Privileged, and the Stack is set to Main.

16 ******************************************************************************

17 * @attention

18 *

19 * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>

20 *

21 * Redistribution and use in source and binary forms, with or without modificat ion,

22 * are permitted provided that the following conditions are met:

23 * 1. Redistributions of source code must retain the above copyright notice,

24 * this list of conditions and the following disclaimer.

25 * 2. Redistributions in binary form must reproduce the above copyright notic e,

26 * this list of conditions and the following disclaimer in the documentati on

27 * and/or other materials provided with the distribution.

28 * 3. Neither the name of STMicroelectronics nor the names of its contributor s

29 * may be used to endorse or promote products derived from this software

30 * without specific prior written permission.

31 *

32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

33 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE A RE

35 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE

36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL

37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR

38 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER

39 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY ,

40 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE US E

41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

42 *

43 ******************************************************************************

44 */

45

46 .syntax unified

47 .cpu cortex-m7

48 .fpu softvfp

49 .thumb

50

51 .global g_pfnVectors

52 .global Default_Handler

53

54 /* start address for the initialization values of the .data section.

55 defined in linker script */

56 .word _sidata

57 /* start address for the .data section. defined in linker script */

58 .word _sdata

59 /* end address for the .data section. defined in linker script */

60 .word _edata

61 /* start address for the .bss section. defined in linker script */

62 .word _sbss

63 /* end address for the .bss section. defined in linker script */

64 .word _ebss

65 /* stack used for SystemInit_ExtMemCtl; always internal RAM used */

66

67 /**

68 * @brief This is the code that gets called when the processor first

69 * starts execution following a reset event. Only the absolutely

70 * necessary set is performed, after which the application

71 * supplied main() routine is called.

72 * @param None

73 * @retval : None

74 */

75

76 .section .text.Reset_Handler

77 .weak Reset_Handler

78 .type Reset_Handler, %function

79 Reset_Handler:

80 ldr sp, =_estack /* set stack pointer */

81

82 /* Copy the data segment initializers from flash to SRAM */

83 movs r1, #0

84 b LoopCopyDataInit

85

86 CopyDataInit:

87 ldr r3, =_sidata

88 ldr r3, [r3, r1]

89 str r3, [r0, r1]

90 adds r1, r1, #4

91

92 LoopCopyDataInit:

93 ldr r0, =_sdata

94 ldr r3, =_edata

95 adds r2, r0, r1

96 cmp r2, r3

97 bcc CopyDataInit

98 ldr r2, =_sbss

99 b LoopFillZerobss

100 /* Zero fill the bss segment. */

101 FillZerobss:

102 movs r3, #0

103 str r3, [r2], #4

104

105 LoopFillZerobss:

106 ldr r3, = _ebss

107 cmp r2, r3

108 bcc FillZerobss

109

110 /* Call the clock system initialization function.*/

111 bl SystemInit

112 /* Call static constructors */

113 bl __libc_init_array

114 /* Call the application's entry point.*/

115 bl main

116 bx lr

117 .size Reset_Handler, .-Reset_Handler

118

119 /**

120 * @brief This is the code that gets called when the processor receives an

121 * unexpected interrupt. This simply enters an infinite loop, preservin g

122 * the system state for examination by a debugger.

123 * @param None

124 * @retval None

125 */

126 .section .text.Default_Handler,"ax",%progbits

127 Default_Handler:

128 Infinite_Loop:

129 b Infinite_Loop

130 .size Default_Handler, .-Default_Handler

131 /******************************************************************************

132 *

133 * The minimal vector table for a Cortex M7. Note that the proper constructs

134 * must be placed on this to ensure that it ends up at physical address

135 * 0x0000.0000.

136 *

137 *******************************************************************************/

138 .section .isr_vector,"a",%progbits

139 .type g_pfnVectors, %object

140 .size g_pfnVectors, .-g_pfnVectors

141

142

143 g_pfnVectors:

144 .word _estack

145 .word Reset_Handler

146

147 .word NMI_Handler

148 .word HardFault_Handler

149 .word MemManage_Handler

150 .word BusFault_Handler

151 .word UsageFault_Handler

152 .word 0

153 .word 0

154 .word 0

155 .word 0

156 .word SVC_Handler

157 .word DebugMon_Handler

158 .word 0

159 .word PendSV_Handler

160 .word SysTick_Handler

161

162 /* External Interrupts */

163 .word WWDG_IRQHandler /* Window WatchDog */

164 .word PVD_IRQHandler /* PVD through EXTI Line detection */

165 .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through t he EXTI line */

166 .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI lin e */

167 .word FLASH_IRQHandler /* FLASH */

168 .word RCC_IRQHandler /* RCC */

169 .word EXTI0_IRQHandler /* EXTI Line0 */

170 .word EXTI1_IRQHandler /* EXTI Line1 */

171 .word EXTI2_IRQHandler /* EXTI Line2 */

172 .word EXTI3_IRQHandler /* EXTI Line3 */

173 .word EXTI4_IRQHandler /* EXTI Line4 */

174 .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */

175 .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */

176 .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */

177 .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */

178 .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */

179 .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */

180 .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */

181 .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */

182 .word CAN1_TX_IRQHandler /* CAN1 TX */

183 .word CAN1_RX0_IRQHandler /* CAN1 RX0 */

184 .word CAN1_RX1_IRQHandler /* CAN1 RX1 */

185 .word CAN1_SCE_IRQHandler /* CAN1 SCE */

186 .word EXTI9_5_IRQHandler /* External Line[9:5]s */

187 .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */

188 .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */

189 .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation an d TIM11 */

190 .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */

191 .word TIM2_IRQHandler /* TIM2 */

192 .word TIM3_IRQHandler /* TIM3 */

193 .word TIM4_IRQHandler /* TIM4 */

194 .word I2C1_EV_IRQHandler /* I2C1 Event */

195 .word I2C1_ER_IRQHandler /* I2C1 Error */

196 .word I2C2_EV_IRQHandler /* I2C2 Event */

197 .word I2C2_ER_IRQHandler /* I2C2 Error */

198 .word SPI1_IRQHandler /* SPI1 */

199 .word SPI2_IRQHandler /* SPI2 */

200 .word USART1_IRQHandler /* USART1 */

201 .word USART2_IRQHandler /* USART2 */

202 .word USART3_IRQHandler /* USART3 */

203 .word EXTI15_10_IRQHandler /* External Line[15:10]s */

204 .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXT I Line */

205 .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */

206 .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */

207 .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */

208 .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation an d TIM14 */

209 .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */

210 .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */

211 .word FMC_IRQHandler /* FMC */

212 .word SDMMC1_IRQHandler /* SDMMC1 */

213 .word TIM5_IRQHandler /* TIM5 */

214 .word SPI3_IRQHandler /* SPI3 */

215 .word UART4_IRQHandler /* UART4 */

216 .word UART5_IRQHandler /* UART5 */

217 .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */

218 .word TIM7_IRQHandler /* TIM7 */

219 .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */

220 .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */

221 .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */

222 .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */

223 .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */

224 .word ETH_IRQHandler /* Ethernet */

225 .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI li ne */

226 .word CAN2_TX_IRQHandler /* CAN2 TX */

227 .word CAN2_RX0_IRQHandler /* CAN2 RX0 */

228 .word CAN2_RX1_IRQHandler /* CAN2 RX1 */

229 .word CAN2_SCE_IRQHandler /* CAN2 SCE */

230 .word OTG_FS_IRQHandler /* USB OTG FS */

231 .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */

232 .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */

233 .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */

234 .word USART6_IRQHandler /* USART6 */

235 .word I2C3_EV_IRQHandler /* I2C3 event */

236 .word I2C3_ER_IRQHandler /* I2C3 error */

237 .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */

238 .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */

239 .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */

240 .word OTG_HS_IRQHandler /* USB OTG HS */

241 .word DCMI_IRQHandler /* DCMI */

242 .word 0 /* Reserved */

243 .word RNG_IRQHandler /* Rng */

244 .word FPU_IRQHandler /* FPU */

245 .word UART7_IRQHandler /* UART7 */

246 .word UART8_IRQHandler /* UART8 */

247 .word SPI4_IRQHandler /* SPI4 */

248 .word SPI5_IRQHandler /* SPI5 */

249 .word SPI6_IRQHandler /* SPI6 */

250 .word SAI1_IRQHandler /* SAI1 */

251 .word LTDC_IRQHandler /* LTDC */

252 .word LTDC_ER_IRQHandler /* LTDC error */

253 .word DMA2D_IRQHandler /* DMA2D */

254 .word SAI2_IRQHandler /* SAI2 */

255 .word QUADSPI_IRQHandler /* QUADSPI */

256 .word LPTIM1_IRQHandler /* LPTIM1 */

257 .word CEC_IRQHandler /* HDMI_CEC */

258 .word I2C4_EV_IRQHandler /* I2C4 Event */

259 .word I2C4_ER_IRQHandler /* I2C4 Error */

260 .word SPDIF_RX_IRQHandler /* SPDIF_RX */

261

262 /*******************************************************************************

263 *

264 * Provide weak aliases for each Exception handler to the Default_Handler.

265 * As they are weak aliases, any function with the same name will override

266 * this definition.

267 *

268 *******************************************************************************/

269 .weak NMI_Handler

270 .thumb_set NMI_Handler,Default_Handler

271

272 .weak HardFault_Handler

273 .thumb_set HardFault_Handler,Default_Handler

274

275 .weak MemManage_Handler

276 .thumb_set MemManage_Handler,Default_Handler

277

278 .weak BusFault_Handler

279 .thumb_set BusFault_Handler,Default_Handler

280

281 .weak UsageFault_Handler

282 .thumb_set UsageFault_Handler,Default_Handler

283

284 .weak SVC_Handler

285 .thumb_set SVC_Handler,Default_Handler

286

287 .weak DebugMon_Handler

288 .thumb_set DebugMon_Handler,Default_Handler

289

290 .weak PendSV_Handler

291 .thumb_set PendSV_Handler,Default_Handler

292

293 .weak SysTick_Handler

294 .thumb_set SysTick_Handler,Default_Handler

295

296 .weak WWDG_IRQHandler

297 .thumb_set WWDG_IRQHandler,Default_Handler

298

299 .weak PVD_IRQHandler

300 .thumb_set PVD_IRQHandler,Default_Handler

301

302 .weak TAMP_STAMP_IRQHandler

303 .thumb_set TAMP_STAMP_IRQHandler,Default_Handler

304

305 .weak RTC_WKUP_IRQHandler

306 .thumb_set RTC_WKUP_IRQHandler,Default_Handler

307

308 .weak FLASH_IRQHandler

309 .thumb_set FLASH_IRQHandler,Default_Handler

310

311 .weak RCC_IRQHandler

312 .thumb_set RCC_IRQHandler,Default_Handler

313

314 .weak EXTI0_IRQHandler

315 .thumb_set EXTI0_IRQHandler,Default_Handler

316

317 .weak EXTI1_IRQHandler

318 .thumb_set EXTI1_IRQHandler,Default_Handler

319

320 .weak EXTI2_IRQHandler

321 .thumb_set EXTI2_IRQHandler,Default_Handler

322

323 .weak EXTI3_IRQHandler

324 .thumb_set EXTI3_IRQHandler,Default_Handler

325

326 .weak EXTI4_IRQHandler

327 .thumb_set EXTI4_IRQHandler,Default_Handler

328

329 .weak DMA1_Stream0_IRQHandler

330 .thumb_set DMA1_Stream0_IRQHandler,Default_Handler

331

332 .weak DMA1_Stream1_IRQHandler

333 .thumb_set DMA1_Stream1_IRQHandler,Default_Handler

334

335 .weak DMA1_Stream2_IRQHandler

336 .thumb_set DMA1_Stream2_IRQHandler,Default_Handler

337

338 .weak DMA1_Stream3_IRQHandler

339 .thumb_set DMA1_Stream3_IRQHandler,Default_Handler

340

341 .weak DMA1_Stream4_IRQHandler

342 .thumb_set DMA1_Stream4_IRQHandler,Default_Handler

343

344 .weak DMA1_Stream5_IRQHandler

345 .thumb_set DMA1_Stream5_IRQHandler,Default_Handler

346

347 .weak DMA1_Stream6_IRQHandler

348 .thumb_set DMA1_Stream6_IRQHandler,Default_Handler

349

350 .weak ADC_IRQHandler

351 .thumb_set ADC_IRQHandler,Default_Handler

352

353 .weak CAN1_TX_IRQHandler

354 .thumb_set CAN1_TX_IRQHandler,Default_Handler

355

356 .weak CAN1_RX0_IRQHandler

357 .thumb_set CAN1_RX0_IRQHandler,Default_Handler

358

359 .weak CAN1_RX1_IRQHandler

360 .thumb_set CAN1_RX1_IRQHandler,Default_Handler

361

362 .weak CAN1_SCE_IRQHandler

363 .thumb_set CAN1_SCE_IRQHandler,Default_Handler

364

365 .weak EXTI9_5_IRQHandler

366 .thumb_set EXTI9_5_IRQHandler,Default_Handler

367

368 .weak TIM1_BRK_TIM9_IRQHandler

369 .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler

370

371 .weak TIM1_UP_TIM10_IRQHandler

372 .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler

373

374 .weak TIM1_TRG_COM_TIM11_IRQHandler

375 .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler

376

377 .weak TIM1_CC_IRQHandler

378 .thumb_set TIM1_CC_IRQHandler,Default_Handler

379

380 .weak TIM2_IRQHandler

381 .thumb_set TIM2_IRQHandler,Default_Handler

382

383 .weak TIM3_IRQHandler

384 .thumb_set TIM3_IRQHandler,Default_Handler

385

386 .weak TIM4_IRQHandler

387 .thumb_set TIM4_IRQHandler,Default_Handler

388

389 .weak I2C1_EV_IRQHandler

390 .thumb_set I2C1_EV_IRQHandler,Default_Handler

391

392 .weak I2C1_ER_IRQHandler

393 .thumb_set I2C1_ER_IRQHandler,Default_Handler

394

395 .weak I2C2_EV_IRQHandler

396 .thumb_set I2C2_EV_IRQHandler,Default_Handler

397

398 .weak I2C2_ER_IRQHandler

399 .thumb_set I2C2_ER_IRQHandler,Default_Handler

400

401 .weak SPI1_IRQHandler

402 .thumb_set SPI1_IRQHandler,Default_Handler

403

404 .weak SPI2_IRQHandler

405 .thumb_set SPI2_IRQHandler,Default_Handler

406

407 .weak USART1_IRQHandler

408 .thumb_set USART1_IRQHandler,Default_Handler

409

410 .weak USART2_IRQHandler

411 .thumb_set USART2_IRQHandler,Default_Handler

412

413 .weak USART3_IRQHandler

414 .thumb_set USART3_IRQHandler,Default_Handler

415

416 .weak EXTI15_10_IRQHandler

417 .thumb_set EXTI15_10_IRQHandler,Default_Handler

418

419 .weak RTC_Alarm_IRQHandler

420 .thumb_set RTC_Alarm_IRQHandler,Default_Handler

421

422 .weak OTG_FS_WKUP_IRQHandler

423 .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler

424

425 .weak TIM8_BRK_TIM12_IRQHandler

426 .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler

427

428 .weak TIM8_UP_TIM13_IRQHandler

429 .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler

430

431 .weak TIM8_TRG_COM_TIM14_IRQHandler

432 .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler

433

434 .weak TIM8_CC_IRQHandler

435 .thumb_set TIM8_CC_IRQHandler,Default_Handler

436

437 .weak DMA1_Stream7_IRQHandler

438 .thumb_set DMA1_Stream7_IRQHandler,Default_Handler

439

440 .weak FMC_IRQHandler

441 .thumb_set FMC_IRQHandler,Default_Handler

442

443 .weak SDMMC1_IRQHandler

444 .thumb_set SDMMC1_IRQHandler,Default_Handler

445

446 .weak TIM5_IRQHandler

447 .thumb_set TIM5_IRQHandler,Default_Handler

448

449 .weak SPI3_IRQHandler

450 .thumb_set SPI3_IRQHandler,Default_Handler

451

452 .weak UART4_IRQHandler

453 .thumb_set UART4_IRQHandler,Default_Handler

454

455 .weak UART5_IRQHandler

456 .thumb_set UART5_IRQHandler,Default_Handler

457

458 .weak TIM6_DAC_IRQHandler

459 .thumb_set TIM6_DAC_IRQHandler,Default_Handler

460

461 .weak TIM7_IRQHandler

462 .thumb_set TIM7_IRQHandler,Default_Handler

463

464 .weak DMA2_Stream0_IRQHandler

465 .thumb_set DMA2_Stream0_IRQHandler,Default_Handler

466

467 .weak DMA2_Stream1_IRQHandler

468 .thumb_set DMA2_Stream1_IRQHandler,Default_Handler

469

470 .weak DMA2_Stream2_IRQHandler

471 .thumb_set DMA2_Stream2_IRQHandler,Default_Handler

472

473 .weak DMA2_Stream3_IRQHandler

474 .thumb_set DMA2_Stream3_IRQHandler,Default_Handler

475

476 .weak DMA2_Stream4_IRQHandler

477 .thumb_set DMA2_Stream4_IRQHandler,Default_Handler

478

479 .weak DMA2_Stream4_IRQHandler

480 .thumb_set DMA2_Stream4_IRQHandler,Default_Handler

481

482 .weak ETH_IRQHandler

483 .thumb_set ETH_IRQHandler,Default_Handler

484

485 .weak ETH_WKUP_IRQHandler

486 .thumb_set ETH_WKUP_IRQHandler,Default_Handler

487

488 .weak CAN2_TX_IRQHandler

489 .thumb_set CAN2_TX_IRQHandler,Default_Handler

490

491 .weak CAN2_RX0_IRQHandler

492 .thumb_set CAN2_RX0_IRQHandler,Default_Handler

493

494 .weak CAN2_RX1_IRQHandler

495 .thumb_set CAN2_RX1_IRQHandler,Default_Handler

496

497 .weak CAN2_SCE_IRQHandler

498 .thumb_set CAN2_SCE_IRQHandler,Default_Handler

499

500 .weak OTG_FS_IRQHandler

501 .thumb_set OTG_FS_IRQHandler,Default_Handler

502

503 .weak DMA2_Stream5_IRQHandler

504 .thumb_set DMA2_Stream5_IRQHandler,Default_Handler

505

506 .weak DMA2_Stream6_IRQHandler

507 .thumb_set DMA2_Stream6_IRQHandler,Default_Handler

508

509 .weak DMA2_Stream7_IRQHandler

510 .thumb_set DMA2_Stream7_IRQHandler,Default_Handler

511

512 .weak USART6_IRQHandler

513 .thumb_set USART6_IRQHandler,Default_Handler

514

515 .weak I2C3_EV_IRQHandler

516 .thumb_set I2C3_EV_IRQHandler,Default_Handler

517

518 .weak I2C3_ER_IRQHandler

519 .thumb_set I2C3_ER_IRQHandler,Default_Handler

520

521 .weak OTG_HS_EP1_OUT_IRQHandler

522 .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler

523

524 .weak OTG_HS_EP1_IN_IRQHandler

525 .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler

526

527 .weak OTG_HS_WKUP_IRQHandler

528 .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler

529

530 .weak OTG_HS_IRQHandler

531 .thumb_set OTG_HS_IRQHandler,Default_Handler

532

533 .weak DCMI_IRQHandler

534 .thumb_set DCMI_IRQHandler,Default_Handler

535

536 .weak RNG_IRQHandler

537 .thumb_set RNG_IRQHandler,Default_Handler

538

539 .weak FPU_IRQHandler

540 .thumb_set FPU_IRQHandler,Default_Handler

541

542 .weak UART7_IRQHandler

543 .thumb_set UART7_IRQHandler,Default_Handler

544

545 .weak UART8_IRQHandler

546 .thumb_set UART8_IRQHandler,Default_Handler

547

548 .weak SPI4_IRQHandler

549 .thumb_set SPI4_IRQHandler,Default_Handler

550

551 .weak SPI5_IRQHandler

552 .thumb_set SPI5_IRQHandler,Default_Handler

553

554 .weak SPI6_IRQHandler

555 .thumb_set SPI6_IRQHandler,Default_Handler

556

557 .weak SAI1_IRQHandler

558 .thumb_set SAI1_IRQHandler,Default_Handler

559

560 .weak LTDC_IRQHandler

561 .thumb_set LTDC_IRQHandler,Default_Handler

562

563 .weak LTDC_ER_IRQHandler

564 .thumb_set LTDC_ER_IRQHandler,Default_Handler

565

566 .weak DMA2D_IRQHandler

567 .thumb_set DMA2D_IRQHandler,Default_Handler

568

569 .weak SAI2_IRQHandler

570 .thumb_set SAI2_IRQHandler,Default_Handler

571

572 .weak QUADSPI_IRQHandler

573 .thumb_set QUADSPI_IRQHandler,Default_Handler

574

575 .weak LPTIM1_IRQHandler

576 .thumb_set LPTIM1_IRQHandler,Default_Handler

577

578 .weak CEC_IRQHandler

579 .thumb_set CEC_IRQHandler,Default_Handler

580

581 .weak I2C4_EV_IRQHandler

582 .thumb_set I2C4_EV_IRQHandler,Default_Handler

583

584 .weak I2C4_ER_IRQHandler

585 .thumb_set I2C4_ER_IRQHandler,Default_Handler

586

587 .weak SPDIF_RX_IRQHandler

588 .thumb_set SPDIF_RX_IRQHandler,Default_Handler

589

590 /********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

591

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