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Issue 1658423002: Fix nits from CL https://codereview.chromium.org/1661633002. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Created 4 years, 10 months ago
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1 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===// 1 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
2 // 2 //
3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
4 // for details. All rights reserved. Use of this source code is governed by a 4 // for details. All rights reserved. Use of this source code is governed by a
5 // BSD-style license that can be found in the LICENSE file. 5 // BSD-style license that can be found in the LICENSE file.
6 // 6 //
7 // Modified by the Subzero authors. 7 // Modified by the Subzero authors.
8 // 8 //
9 //===----------------------------------------------------------------------===// 9 //===----------------------------------------------------------------------===//
10 // 10 //
(...skipping 2738 matching lines...)
2749 constexpr IValueT VmuldOpcode = B21; 2749 constexpr IValueT VmuldOpcode = B21;
2750 emitVFPddd(Cond, VmuldOpcode, OpDd, OpDn, OpDm, Vmuld); 2750 emitVFPddd(Cond, VmuldOpcode, OpDd, OpDn, OpDm, Vmuld);
2751 } 2751 }
2752 2752
2753 void AssemblerARM32::vorrq(const Operand *OpQd, const Operand *OpQm, 2753 void AssemblerARM32::vorrq(const Operand *OpQd, const Operand *OpQm,
2754 const Operand *OpQn) { 2754 const Operand *OpQn) {
2755 // VORR (register) - ARM section A8.8.360, encoding A1: 2755 // VORR (register) - ARM section A8.8.360, encoding A1:
2756 // vorr <Qd>, <Qn>, <Qm> 2756 // vorr <Qd>, <Qn>, <Qm>
2757 // 2757 //
2758 // 111100100D10nnn0ddd00001N1M1mmm0 where Dddd=OpQd, Nnnn=OpQm, and Mmmm=OpQm. 2758 // 111100100D10nnn0ddd00001N1M1mmm0 where Dddd=OpQd, Nnnn=OpQm, and Mmmm=OpQm.
2759 constexpr const char *Vorrq = "vandq"; 2759 constexpr const char *Vorrq = "vorrq";
2760 constexpr IValueT VorrqOpcode = B21 | B8 | B4; 2760 constexpr IValueT VorrqOpcode = B21 | B8 | B4;
2761 constexpr Type ElmtTy = IceType_i8; 2761 constexpr Type ElmtTy = IceType_i8;
2762 emitSIMDqqq(VorrqOpcode, ElmtTy, OpQd, OpQm, OpQn, Vorrq); 2762 emitSIMDqqq(VorrqOpcode, ElmtTy, OpQd, OpQm, OpQn, Vorrq);
2763 } 2763 }
2764 2764
2765 void AssemblerARM32::vstrd(const Operand *OpDd, const Operand *OpAddress, 2765 void AssemblerARM32::vstrd(const Operand *OpDd, const Operand *OpAddress,
2766 CondARM32::Cond Cond, const TargetInfo &TInfo) { 2766 CondARM32::Cond Cond, const TargetInfo &TInfo) {
2767 // VSTR - ARM section A8.8.413, encoding A1: 2767 // VSTR - ARM section A8.8.413, encoding A1:
2768 // vstr<c> <Dd>, [<Rn>{, #+/-<Imm>}] 2768 // vstr<c> <Dd>, [<Rn>{, #+/-<Imm>}]
2769 // 2769 //
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2921 constexpr const char *Vsqrts = "vsqrts"; 2921 constexpr const char *Vsqrts = "vsqrts";
2922 IValueT Sd = encodeSRegister(OpSd, "Sd", Vsqrts); 2922 IValueT Sd = encodeSRegister(OpSd, "Sd", Vsqrts);
2923 IValueT Sm = encodeSRegister(OpSm, "Sm", Vsqrts); 2923 IValueT Sm = encodeSRegister(OpSm, "Sm", Vsqrts);
2924 constexpr IValueT VsqrtsOpcode = B23 | B21 | B20 | B16 | B7 | B6; 2924 constexpr IValueT VsqrtsOpcode = B23 | B21 | B20 | B16 | B7 | B6;
2925 constexpr IValueT S0 = 0; 2925 constexpr IValueT S0 = 0;
2926 emitVFPsss(Cond, VsqrtsOpcode, Sd, S0, Sm); 2926 emitVFPsss(Cond, VsqrtsOpcode, Sd, S0, Sm);
2927 } 2927 }
2928 2928
2929 } // end of namespace ARM32 2929 } // end of namespace ARM32
2930 } // end of namespace Ice 2930 } // end of namespace Ice
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