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Side by Side Diff: src/IceAssemblerARM32.cpp

Issue 1657353002: Add VAND to the integrated ARM assembler. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Fix nits. Created 4 years, 10 months ago
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1 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===// 1 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
2 // 2 //
3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
4 // for details. All rights reserved. Use of this source code is governed by a 4 // for details. All rights reserved. Use of this source code is governed by a
5 // BSD-style license that can be found in the LICENSE file. 5 // BSD-style license that can be found in the LICENSE file.
6 // 6 //
7 // Modified by the Subzero authors. 7 // Modified by the Subzero authors.
8 // 8 //
9 //===----------------------------------------------------------------------===// 9 //===----------------------------------------------------------------------===//
10 // 10 //
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2181 // VADD (floating-point) - ARM section A8.8.283, encoding A2: 2181 // VADD (floating-point) - ARM section A8.8.283, encoding A2:
2182 // vadd<c>.f64 <Dd>, <Dn>, <Dm> 2182 // vadd<c>.f64 <Dd>, <Dn>, <Dm>
2183 // 2183 //
2184 // cccc11100D11nnnndddd101sN0M0mmmm where cccc=Cond, s=1, Ddddd=Rd, Nnnnn=Rn, 2184 // cccc11100D11nnnndddd101sN0M0mmmm where cccc=Cond, s=1, Ddddd=Rd, Nnnnn=Rn,
2185 // and Mmmmm=Rm. 2185 // and Mmmmm=Rm.
2186 constexpr const char *Vaddd = "vaddd"; 2186 constexpr const char *Vaddd = "vaddd";
2187 constexpr IValueT VadddOpcode = B21 | B20; 2187 constexpr IValueT VadddOpcode = B21 | B20;
2188 emitVFPddd(Cond, VadddOpcode, OpDd, OpDn, OpDm, Vaddd); 2188 emitVFPddd(Cond, VadddOpcode, OpDd, OpDn, OpDm, Vaddd);
2189 } 2189 }
2190 2190
2191 void AssemblerARM32::vandq(const Operand *OpQd, const Operand *OpQm,
2192 const Operand *OpQn) {
2193 // VAND (register) - ARM section A8.8.287, encoding A1:
2194 // vand.<dt> <Qd>, <Qn>, <Qm>
2195 //
2196 // 111100100D00nnn0ddd00001N1M1mmm0 where Dddd=OpQd, Nnnn=OpQm, and Mmmm=OpQm.
2197 constexpr const char *Vandqi = "vandqi";
2198 constexpr IValueT VandqiOpcode = B8 | B4;
2199 constexpr Type ElmtTy = IceType_i8;
2200 emitSIMDqqq(VandqiOpcode, ElmtTy, OpQd, OpQm, OpQn, Vandqi);
2201 }
2202
2191 void AssemblerARM32::vcmpd(const Operand *OpDd, const Operand *OpDm, 2203 void AssemblerARM32::vcmpd(const Operand *OpDd, const Operand *OpDm,
2192 CondARM32::Cond Cond) { 2204 CondARM32::Cond Cond) {
2193 constexpr const char *Vcmpd = "vcmpd"; 2205 constexpr const char *Vcmpd = "vcmpd";
2194 IValueT Dd = encodeDRegister(OpDd, "Dd", Vcmpd); 2206 IValueT Dd = encodeDRegister(OpDd, "Dd", Vcmpd);
2195 IValueT Dm = encodeDRegister(OpDm, "Dm", Vcmpd); 2207 IValueT Dm = encodeDRegister(OpDm, "Dm", Vcmpd);
2196 constexpr IValueT VcmpdOpcode = B23 | B21 | B20 | B18 | B6; 2208 constexpr IValueT VcmpdOpcode = B23 | B21 | B20 | B18 | B6;
2197 constexpr IValueT Dn = 0; 2209 constexpr IValueT Dn = 0;
2198 emitVFPddd(Cond, VcmpdOpcode, Dd, Dn, Dm); 2210 emitVFPddd(Cond, VcmpdOpcode, Dd, Dn, Dm);
2199 } 2211 }
2200 2212
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2869 constexpr const char *Vsqrts = "vsqrts"; 2881 constexpr const char *Vsqrts = "vsqrts";
2870 IValueT Sd = encodeSRegister(OpSd, "Sd", Vsqrts); 2882 IValueT Sd = encodeSRegister(OpSd, "Sd", Vsqrts);
2871 IValueT Sm = encodeSRegister(OpSm, "Sm", Vsqrts); 2883 IValueT Sm = encodeSRegister(OpSm, "Sm", Vsqrts);
2872 constexpr IValueT VsqrtsOpcode = B23 | B21 | B20 | B16 | B7 | B6; 2884 constexpr IValueT VsqrtsOpcode = B23 | B21 | B20 | B16 | B7 | B6;
2873 constexpr IValueT S0 = 0; 2885 constexpr IValueT S0 = 0;
2874 emitVFPsss(Cond, VsqrtsOpcode, Sd, S0, Sm); 2886 emitVFPsss(Cond, VsqrtsOpcode, Sd, S0, Sm);
2875 } 2887 }
2876 2888
2877 } // end of namespace ARM32 2889 } // end of namespace ARM32
2878 } // end of namespace Ice 2890 } // end of namespace Ice
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