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Unified Diff: src/IceAssemblerARM32.cpp

Issue 1657193003: Add FABS intrinsic to the integrated ARM assembler. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Format. Created 4 years, 11 months ago
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Index: src/IceAssemblerARM32.cpp
diff --git a/src/IceAssemblerARM32.cpp b/src/IceAssemblerARM32.cpp
index 9325b4ed17bb21e7a2712324f31cb66c8bd5157c..df1c499c631aa744b9ff55cd6aa7e04e36596eb3 100644
--- a/src/IceAssemblerARM32.cpp
+++ b/src/IceAssemblerARM32.cpp
@@ -2141,6 +2141,34 @@ void AssemblerARM32::uxt(const Operand *OpRd, const Operand *OpSrc0,
emitSignExtend(Cond, UxtOpcode, OpRd, OpSrc0, UxtName);
}
+void AssemblerARM32::vabss(const Operand *OpSd, const Operand *OpSm,
+ CondARM32::Cond Cond) {
+ // VABS - ARM section A8.8.280, encoding A2:
+ // vabs<c>.f32 <Sd>, <Sm>
+ //
+ // cccc11101D110000dddd101011M0mmmm where cccc=Cond, ddddD=Sd, and mmmmM=Sm.
+ constexpr const char *Vabss = "vabss";
+ IValueT Sd = encodeSRegister(OpSd, "Sd", Vabss);
+ IValueT Sm = encodeSRegister(OpSm, "Sm", Vabss);
+ constexpr IValueT S0 = 0;
+ constexpr IValueT VabssOpcode = B23 | B21 | B20 | B7 | B6;
+ emitVFPsss(Cond, VabssOpcode, Sd, S0, Sm);
+}
+
+void AssemblerARM32::vabsd(const Operand *OpDd, const Operand *OpDm,
+ CondARM32::Cond Cond) {
+ // VABS - ARM section A8.8.280, encoding A2:
+ // vabs<c>.f64 <Dd>, <Dm>
+ //
+ // cccc11101D110000dddd101111M0mmmm where cccc=Cond, Ddddd=Dd, and Mmmmm=Dm.
+ constexpr const char *Vabsd = "vabsd";
+ IValueT Dd = encodeDRegister(OpDd, "Dd", Vabsd);
+ IValueT Dm = encodeDRegister(OpDm, "Dm", Vabsd);
+ constexpr IValueT D0 = 0;
+ constexpr IValueT VabsdOpcode = B23 | B21 | B20 | B7 | B6;
+ emitVFPddd(Cond, VabsdOpcode, Dd, D0, Dm);
+}
+
void AssemblerARM32::vadds(const Operand *OpSd, const Operand *OpSn,
const Operand *OpSm, CondARM32::Cond Cond) {
// VADD (floating-point) - ARM section A8.8.283, encoding A2:
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