Add FABS intrinsic to the integrated ARM assembler.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 2123 matching lines @@
   emitMulOp(Cond, UmullOpcode, RdLo, RdHi, Rn, Rm, SetFlags);
 }
 
 void AssemblerARM32::uxt(const Operand *OpRd, const Operand *OpSrc0,
                          CondARM32::Cond Cond) {
   constexpr const char *UxtName = "uxt";
   constexpr IValueT UxtOpcode = B26 | B25 | B23 | B22 | B21;
   emitSignExtend(Cond, UxtOpcode, OpRd, OpSrc0, UxtName);
 }
 
+void AssemblerARM32::vabss(const Operand *OpSd, const Operand *OpSm,
+                           CondARM32::Cond Cond) {
+  // VABS - ARM section A8.8.280, encoding A2:
+  //   vabs<c>.f32 <Sd>, <Sm>
+  //
+  // cccc11101D110000dddd101011M0mmmm where cccc=Cond, ddddD=Sd, and mmmmM=Sm.
+  constexpr const char *Vabss = "vabss";
+  IValueT Sd = encodeSRegister(OpSd, "Sd", Vabss);
+  IValueT Sm = encodeSRegister(OpSm, "Sm", Vabss);
+  constexpr IValueT S0 = 0;
+  constexpr IValueT VabssOpcode = B23 | B21 | B20 | B7 | B6;
+  emitVFPsss(Cond, VabssOpcode, Sd, S0, Sm);
+}
+
+void AssemblerARM32::vabsd(const Operand *OpDd, const Operand *OpDm,
+                           CondARM32::Cond Cond) {
+  // VABS - ARM section A8.8.280, encoding A2:
+  //   vabs<c>.f64 <Dd>, <Dm>
+  //
+  // cccc11101D110000dddd101111M0mmmm where cccc=Cond, Ddddd=Dd, and Mmmmm=Dm.
+  constexpr const char *Vabsd = "vabsd";
+  IValueT Dd = encodeDRegister(OpDd, "Dd", Vabsd);
+  IValueT Dm = encodeDRegister(OpDm, "Dm", Vabsd);
+  constexpr IValueT D0 = 0;
+  constexpr IValueT VabsdOpcode = B23 | B21 | B20 | B7 | B6;
+  emitVFPddd(Cond, VabsdOpcode, Dd, D0, Dm);
+}
+
 void AssemblerARM32::vadds(const Operand *OpSd, const Operand *OpSn,
                            const Operand *OpSm, CondARM32::Cond Cond) {
   // VADD (floating-point) - ARM section A8.8.283, encoding A2:
   //   vadd<c>.f32 <Sd>, <Sn>, <Sm>
   //
   // cccc11100D11nnnndddd101sN0M0mmmm where cccc=Cond, s=0, ddddD=Rd, nnnnN=Rn,
   // and mmmmM=Rm.
   constexpr const char *Vadds = "vadds";
   constexpr IValueT VaddsOpcode = B21 | B20;
   emitVFPsss(Cond, VaddsOpcode, OpSd, OpSn, OpSm, Vadds);
@@ skipping 715 matching lines @@
   constexpr const char *Vsqrts = "vsqrts";
   IValueT Sd = encodeSRegister(OpSd, "Sd", Vsqrts);
   IValueT Sm = encodeSRegister(OpSm, "Sm", Vsqrts);
   constexpr IValueT VsqrtsOpcode = B23 | B21 | B20 | B16 | B7 | B6;
   constexpr IValueT S0 = 0;
   emitVFPsss(Cond, VsqrtsOpcode, Sd, S0, Sm);
 }
 
 } // end of namespace ARM32
 } // end of namespace Ice