Add vector VEOR instruction to the integrated ARM assembler.

src/IceTargetLoweringARM32.cpp

 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 2971 matching lines @@
       _vorr(T, Src0R, Src1R);
     } else {
       Operand *Src1RF = Srcs.src1RF(this);
       _orr(T, Src0R, Src1RF);
     }
     _mov(Dest, T);
     return;
   }
   case InstArithmetic::Xor: {
     Variable *Src0R = Srcs.src0R(this);
+    assert(isIntegerType(DestTy));
     if (isVectorType(DestTy)) {
       Variable *Src1R = legalizeToReg(Src1);
       _veor(T, Src0R, Src1R);
     } else {
       Operand *Src1RF = Srcs.src1RF(this);
       _eor(T, Src0R, Src1RF);
     }
     _mov(Dest, T);
     return;
   }
@@ skipping 3520 matching lines @@
   Str << ".eabi_attribute 14, 3   @ Tag_ABI_PCS_R9_use: Not used\n";
 }
 
 llvm::SmallBitVector TargetARM32::TypeToRegisterSet[RegARM32::RCARM32_NUM];
 llvm::SmallBitVector
     TargetARM32::TypeToRegisterSetUnfiltered[RegARM32::RCARM32_NUM];
 llvm::SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM];
 
 } // end of namespace ARM32
 } // end of namespace Ice