Add vector VEOR instruction to the integrated ARM assembler.

src/IceInstARM32.cpp

 //===- subzero/src/IceInstARM32.cpp - ARM32 instruction implementation ----===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 662 matching lines @@
     Asm->vdivd(getDest(), getSrc(0), getSrc(1), CondARM32::AL);
     break;
   }
   assert(!Asm->needsTextFixup());
 }
 
 template <> void InstARM32Veor::emitIAS(const Cfg *Func) const {
   auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
   const Variable *Dest = getDest();
   if (isVectorType(Dest->getType())) {
-    // TODO(kschimpf): Add support for this case
-    emitUsingTextFixup(Func);
+    Asm->veorq(Dest, getSrc(0), getSrc(1));
+    assert(!Asm->needsTextFixup());
     return;
   }
   assert(Dest->getType() == IceType_f64);
   Asm->veord(Dest, getSrc(0), getSrc(1));
   assert(!Asm->needsTextFixup());
 }
 
 template <> void InstARM32Vmla::emitIAS(const Cfg *Func) const {
   // Note: Dest == getSrc(0) for four address FP instructions.
   assert(getSrcSize() == 3);
@@ skipping 1831 matching lines @@
 
 template class InstARM32FourAddrGPR<InstARM32::Mla>;
 template class InstARM32FourAddrGPR<InstARM32::Mls>;
 
 template class InstARM32CmpLike<InstARM32::Cmn>;
 template class InstARM32CmpLike<InstARM32::Cmp>;
 template class InstARM32CmpLike<InstARM32::Tst>;
 
 } // end of namespace ARM32
 } // end of namespace Ice