Subzero: ARM32: lowering of vector insert and extract.

src/IceTargetLoweringARM32.cpp

 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 279 matching lines @@
       CPUFeatures(Func->getContext()->getFlags()) {}
 
 void TargetARM32::staticInit(GlobalContext *Ctx) {
 
   // Limit this size (or do all bitsets need to be the same width)???
   llvm::SmallBitVector IntegerRegisters(RegARM32::Reg_NUM);
   llvm::SmallBitVector I64PairRegisters(RegARM32::Reg_NUM);
   llvm::SmallBitVector Float32Registers(RegARM32::Reg_NUM);
   llvm::SmallBitVector Float64Registers(RegARM32::Reg_NUM);
   llvm::SmallBitVector VectorRegisters(RegARM32::Reg_NUM);
+  llvm::SmallBitVector QtoSRegisters(RegARM32::Reg_NUM);
   llvm::SmallBitVector InvalidRegisters(RegARM32::Reg_NUM);
   for (int i = 0; i < RegARM32::Reg_NUM; ++i) {
     const auto &Entry = RegARM32::RegTable[i];
     IntegerRegisters[i] = Entry.IsInt;
     I64PairRegisters[i] = Entry.IsI64Pair;
     Float32Registers[i] = Entry.IsFP32;
     Float64Registers[i] = Entry.IsFP64;
     VectorRegisters[i] = Entry.IsVec128;
     RegisterAliases[i].resize(RegARM32::Reg_NUM);
+    QtoSRegisters[i] = Entry.IsVec128 && i < RegARM32::Reg_q8;
     for (int j = 0; j < Entry.NumAliases; ++j) {
       assert(i == j || !RegisterAliases[i][Entry.Aliases[j]]);
       RegisterAliases[i].set(Entry.Aliases[j]);
     }
     assert(RegisterAliases[i][i]);
     if (Entry.CCArg <= 0) {
       continue;
     }
     if (Entry.IsGPR) {
       GPRArgInitializer[Entry.CCArg - 1] = i;
@@ skipping 15 matching lines @@
   TypeToRegisterSet[IceType_i64] = I64PairRegisters;
   TypeToRegisterSet[IceType_f32] = Float32Registers;
   TypeToRegisterSet[IceType_f64] = Float64Registers;
   TypeToRegisterSet[IceType_v4i1] = VectorRegisters;
   TypeToRegisterSet[IceType_v8i1] = VectorRegisters;
   TypeToRegisterSet[IceType_v16i1] = VectorRegisters;
   TypeToRegisterSet[IceType_v16i8] = VectorRegisters;
   TypeToRegisterSet[IceType_v8i16] = VectorRegisters;
   TypeToRegisterSet[IceType_v4i32] = VectorRegisters;
   TypeToRegisterSet[IceType_v4f32] = VectorRegisters;
+  TypeToRegisterSet[RegARM32::RCARM32_QtoS] = QtoSRegisters;
 
   for (size_t i = 0; i < llvm::array_lengthof(TypeToRegisterSet); ++i)
     TypeToRegisterSetUnfiltered[i] = TypeToRegisterSet[i];
 
   filterTypeToRegisterSet(
       Ctx, RegARM32::Reg_NUM, TypeToRegisterSet,
       llvm::array_lengthof(TypeToRegisterSet), [](int32_t RegNum) -> IceString {
         // This function simply removes ", " from the register name.
         IceString Name = RegARM32::getRegName(RegNum);
         constexpr const char RegSeparator[] = ", ";
@@ skipping 3469 matching lines @@
     case IceType_v4i32: {
       UnimplementedLoweringError(this, Inst);
       break;
     }
     }
     break;
   }
   }
 }
 
-void TargetARM32::lowerExtractElement(const InstExtractElement *Inst) {
-  UnimplementedLoweringError(this, Inst);
+void TargetARM32::lowerExtractElement(const InstExtractElement *Instr) {
+  Variable *Dest = Instr->getDest();
+  auto DestTy = Dest->getType();
+
+  if (Dest->isRematerializable()) {
+    Context.insert<InstFakeDef>(Dest);
+    return;
+  }
+
+  Variable *Src0 = legalizeToReg(Instr->getSrc(0));
+  Operand *Src1 = Instr->getSrc(1);
+
+  if (const auto *Imm = llvm::dyn_cast<ConstantInteger32>(Src1)) {
+    const uint32_t Index = Imm->getValue();
+    Variable *T = makeReg(DestTy);
+    Variable *TSrc0 = makeReg(Src0->getType());

[Jim Stichnoth, 2016/02/03 22:32:21]

Bikeshed: the name "TSrc0" strikes me as unlike any other variable name here. 
I'm too lazy to figure out a better name, any ideas John?

+
+    if (isFloatingType(DestTy)) {
+      // We need to make sure the source is in a suitable register.
+      TSrc0->setRegClass(RegARM32::RCARM32_QtoS);

[Jim Stichnoth, 2016/02/03 22:32:21]

Another possibility is to move more stuff into this conditional:
if (isFloatingType(DestTy)) {
  Variable *TSrc0 = makeReg(Src0->getType());
  TSrc0->setRegClass(RegARM32::RCARM32_QtoS);
  _mov(TSrc0, Src0);
  Src0 = TSrc0;
}

[John, 2016/02/04 15:23:57]

+1

+    }
+
+    _mov(TSrc0, Src0);
+    _extractelement(T, TSrc0, Index);
+    _mov(Dest, T);
+    return;
+  } else {
+    assert(false && "extractelement requires a constant index");
+  }
 }
 
 namespace {
 // Validates FCMPARM32_TABLE's declaration w.r.t. InstFcmp::FCondition ordering
 // (and naming).
 enum {
 #define X(val, CC0, CC1) _fcmp_ll_##val,
   FCMPARM32_TABLE
 #undef X
       _fcmp_ll_NUM
@@ skipping 373 matching lines @@
   _mov(T, _0);
   CondWhenTrue Cond = lowerIcmpCond(Inst);
   _mov_redefined(T, _1, Cond.WhenTrue0);
   _mov(Dest, T);
 
   assert(Cond.WhenTrue1 == CondARM32::kNone);
 
   return;
 }
 
-void TargetARM32::lowerInsertElement(const InstInsertElement *Inst) {
-  UnimplementedLoweringError(this, Inst);
+void TargetARM32::lowerInsertElement(const InstInsertElement *Instr) {
+  Variable *Dest = Instr->getDest();
+  auto DestTy = Dest->getType();
+
+  if (Dest->isRematerializable()) {
+    Context.insert<InstFakeDef>(Dest);
+    return;
+  }
+
+  Variable *Src0 = legalizeToReg(Instr->getSrc(0));
+  Variable *Src1 = legalizeToReg(Instr->getSrc(1));
+  Operand *Src2 = Instr->getSrc(2);
+
+  if (const auto *Imm = llvm::dyn_cast<ConstantInteger32>(Src2)) {
+    auto Index = Imm->getValue();
+    Variable *T = makeReg(DestTy);
+
+    if (isFloatingType(DestTy)) {
+      T->setRegClass(RegARM32::RCARM32_QtoS);
+    }
+
+    _mov(T, Src0);
+    _insertelement(T, Src1, Index);
+    _set_dest_redefined();
+    _mov(Dest, T);
+    return;
+  }
+  assert(false && "insertelement requires a constant index");
 }
 
 namespace {
 inline uint64_t getConstantMemoryOrder(Operand *Opnd) {
   if (auto *Integer = llvm::dyn_cast<ConstantInteger32>(Opnd))
     return Integer->getValue();
   return Intrinsics::MemoryOrderInvalid;
 }
 } // end of anonymous namespace
 
@@ skipping 2276 matching lines @@
   Str << ".eabi_attribute 14, 3   @ Tag_ABI_PCS_R9_use: Not used\n";
 }
 
 llvm::SmallBitVector TargetARM32::TypeToRegisterSet[RegARM32::RCARM32_NUM];
 llvm::SmallBitVector
     TargetARM32::TypeToRegisterSetUnfiltered[RegARM32::RCARM32_NUM];
 llvm::SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM];
 
 } // end of namespace ARM32
 } // end of namespace Ice