Subzero: ARM32: lowering of vector insert and extract.

src/IceInstARM32.cpp

 //===- subzero/src/IceInstARM32.cpp - ARM32 instruction implementation ----===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// \brief Implements the InstARM32 and OperandARM32 classes, primarily the
 /// constructors and the dump()/emit() methods.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "IceInstARM32.h"
 
 #include "IceAssemblerARM32.h"
 #include "IceCfg.h"
 #include "IceCfgNode.h"
 #include "IceInst.h"
 #include "IceOperand.h"
-#include "IceRegistersARM32.h"
 #include "IceTargetLoweringARM32.h"
 
 namespace Ice {
 namespace ARM32 {
 
 namespace {
 
 // maximum number of registers allowed in vpush/vpop.
 static constexpr SizeT VpushVpopMaxConsecRegs = 16;
 
@@ skipping 940 matching lines @@
   }
 
   if (Src64 == nullptr) {
     addSource(Src);
   } else {
     addSource(Src64->getLo());
     addSource(Src64->getHi());
   }
 }
 
+RegARM32::AllRegisters
+InstARM32ExtractInsert::getDRegister(const Variable *Src) const {
+  assert(Src->hasReg());
+  RegARM32::AllRegisters SrcReg = (RegARM32::AllRegisters)Src->getRegNum();
+
+  const RegARM32::RegTableType &SrcEntry = RegARM32::RegTable[SrcReg];
+  assert(SrcEntry.IsVec128);
+
+  const uint32_t NumElements = typeNumElements(Src->getType());
+
+  // This code assumes the Aliases list goes Q_n, S_2n, S_2n+1. The asserts in
+  // the next two branches help to check that this is still true.
+  if (Index < NumElements / 2) {
+    // TODO(jpp): find a way to do this that doesn't rely on ordering of the
+    // alias list.
+    SrcReg = (RegARM32::AllRegisters)SrcEntry.Aliases[1];
+    // We have a Q register that's made up of two D registers. This assert is
+    // to help ensure that we picked the right D register.
+    assert(RegARM32::RegTable[SrcEntry.Aliases[1]].Encoding + 1 ==
+           RegARM32::RegTable[SrcEntry.Aliases[2]].Encoding);
+  } else {
+    // TODO(jpp): find a way to do this that doesn't rely on ordering of the
+    // alias list.
+    SrcReg = (RegARM32::AllRegisters)SrcEntry.Aliases[2];
+    // We have a Q register that's made up of two D registers. This assert is
+    // to help ensure that we picked the right D register.
+    assert(RegARM32::RegTable[SrcEntry.Aliases[2]].Encoding - 1 ==
+           RegARM32::RegTable[SrcEntry.Aliases[1]].Encoding);
+  }
+  return SrcReg;
+}
+
+uint32_t InstARM32ExtractInsert::getDIndex(uint32_t NumElements) const {
+  if (Index < NumElements / 2) {
+    return Index;
+  } else {
+    return Index - (NumElements / 2);
+  }
+}
+
+RegARM32::AllRegisters
+InstARM32ExtractInsert::getSRegister(const Variable *Src) const {
+  assert(Src->hasReg());
+  auto SrcReg = Src->getRegNum();
+
+  // For floating point values, we need to be allocated to Q0 - Q7, so we can
+  // directly access the value we want as one of the S registers.
+  assert(Src->getType() == IceType_v4f32 && SrcReg < RegARM32::Reg_q8);
+
+  // This part assumes the register alias list is goes q0, d0, d1, s0, s1, s2,
+  // s3.
+  assert(Index < 4);
+
+  // TODO(jpp): find a way to do this that doesn't rely on ordering of the alias
+  // list.
+  return (RegARM32::AllRegisters)RegARM32::RegTable[SrcReg].Aliases[Index + 3];
+}
+
+void InstARM32Extract::emit(const Cfg *Func) const {
+  auto &Str = Func->getContext()->getStrEmit();

[Jim Stichnoth, 2016/02/03 22:32:21]

Ostream &Str

+  auto DestTy = getDest()->getType();

[Jim Stichnoth, 2016/02/03 22:32:21]

const Type DestTy

+
+  auto Src = llvm::dyn_cast<Variable>(getSrc(0));

[Jim Stichnoth, 2016/02/03 22:32:21]

auto *

+
+  if (isIntegerType(DestTy)) {
+    Str << "\t"
+        << "vmov" << getPredicate();
+    auto BitSize = typeWidthInBytes(DestTy) * CHAR_BIT;
+    if (BitSize < 32) {
+      Str << ".s" << BitSize;
+    } else {
+      Str << "." << BitSize;
+    }
+    Str << "\t";
+    getDest()->emit(Func);
+    Str << ", ";
+
+    auto VectorSize = typeNumElements(Src->getType());
+
+    auto SrcReg = getDRegister(Src);
+
+    Str << RegARM32::RegTable[SrcReg].Name;
+    Str << "[" << getDIndex(VectorSize) << "]";
+  } else if (isFloatingType(DestTy)) {
+    auto SrcReg = getSRegister(Src);
+
+    Str << "\t"
+        << "vmov" << getPredicate() << ".f32"
+        << "\t";
+    getDest()->emit(Func);
+    Str << ", " << RegARM32::RegTable[SrcReg].Name;
+  } else {
+    assert(false && "Invalid extract type");
+  }
+}
+
+void InstARM32Insert::emit(const Cfg *Func) const {
+  Ostream &Str = Func->getContext()->getStrEmit();
+  const Variable *Dest = getDest();
+  const Type DestTy = getDest()->getType();
+
+  assert(llvm::isa<Variable>(getSrc(0)));
+  auto Src = llvm::dyn_cast<Variable>(getSrc(0));
+
+  if (isIntegerType(DestTy)) {
+    Str << "\t"
+        << "vmov" << getPredicate();
+    auto BitSize = typeWidthInBytes(typeElementType(DestTy)) * CHAR_BIT;
+    Str << "." << BitSize << "\t";
+
+    auto VectorSize = typeNumElements(DestTy);
+    auto DestReg = getDRegister(Dest);
+    auto Index = getDIndex(VectorSize);
+    Str << RegARM32::RegTable[DestReg].Name;
+    Str << "[" << Index << "], ";
+    Src->emit(Func);
+  } else if (isFloatingType(DestTy)) {
+    Str << "\t"
+        << "vmov" << getPredicate() << ".f32"
+        << "\t";
+    auto DestReg = getSRegister(Dest);
+    Str << RegARM32::RegTable[DestReg].Name << ", ";
+    Src->emit(Func);
+  } else {
+    assert(false && "Invalid insert type");
+  }
+}
+
 template <InstARM32::InstKindARM32 K>
 void InstARM32CmpLike<K>::emitIAS(const Cfg *Func) const {
   emitUsingTextFixup(Func);
 }
 
 template <> void InstARM32Cmn::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 2);
   auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
   Asm->cmn(getSrc(0), getSrc(1), getPredicate());
   if (Asm->needsTextFixup())
@@ skipping 1456 matching lines @@
 
 template class InstARM32FourAddrGPR<InstARM32::Mla>;
 template class InstARM32FourAddrGPR<InstARM32::Mls>;
 
 template class InstARM32CmpLike<InstARM32::Cmn>;
 template class InstARM32CmpLike<InstARM32::Cmp>;
 template class InstARM32CmpLike<InstARM32::Tst>;
 
 } // end of namespace ARM32
 } // end of namespace Ice