Subzero: ARM32: lowering of vector insert and extract.

src/IceTargetLoweringARM32.cpp

 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 280 matching lines @@
 
 void TargetARM32::staticInit(GlobalContext *Ctx) {
 
   // Limit this size (or do all bitsets need to be the same width)???
   llvm::SmallBitVector IntegerRegisters(RegARM32::Reg_NUM);
   llvm::SmallBitVector I64PairRegisters(RegARM32::Reg_NUM);
   llvm::SmallBitVector Float32Registers(RegARM32::Reg_NUM);
   llvm::SmallBitVector Float64Registers(RegARM32::Reg_NUM);
   llvm::SmallBitVector VectorRegisters(RegARM32::Reg_NUM);
   llvm::SmallBitVector InvalidRegisters(RegARM32::Reg_NUM);
+  llvm::SmallBitVector QtoSRegisters(RegARM32::Reg_NUM);

[Jim Stichnoth, 2016/02/03 15:28:37]

I would list this before InvalidRegisters.

[Eric Holk, 2016/02/03 21:02:22]

Done.

   for (int i = 0; i < RegARM32::Reg_NUM; ++i) {
     const auto &Entry = RegARM32::RegTable[i];
     IntegerRegisters[i] = Entry.IsInt;
     I64PairRegisters[i] = Entry.IsI64Pair;
     Float32Registers[i] = Entry.IsFP32;
     Float64Registers[i] = Entry.IsFP64;
     VectorRegisters[i] = Entry.IsVec128;
     RegisterAliases[i].resize(RegARM32::Reg_NUM);
+    QtoSRegisters[i] = Entry.IsVec128 && i < RegARM32::Reg_q8;
     for (int j = 0; j < Entry.NumAliases; ++j) {
       assert(i == j || !RegisterAliases[i][Entry.Aliases[j]]);
       RegisterAliases[i].set(Entry.Aliases[j]);
     }
     assert(RegisterAliases[i][i]);
     if (Entry.CCArg <= 0) {
       continue;
     }
     if (Entry.IsGPR) {
       GPRArgInitializer[Entry.CCArg - 1] = i;
@@ skipping 15 matching lines @@
   TypeToRegisterSet[IceType_i64] = I64PairRegisters;
   TypeToRegisterSet[IceType_f32] = Float32Registers;
   TypeToRegisterSet[IceType_f64] = Float64Registers;
   TypeToRegisterSet[IceType_v4i1] = VectorRegisters;
   TypeToRegisterSet[IceType_v8i1] = VectorRegisters;
   TypeToRegisterSet[IceType_v16i1] = VectorRegisters;
   TypeToRegisterSet[IceType_v16i8] = VectorRegisters;
   TypeToRegisterSet[IceType_v8i16] = VectorRegisters;
   TypeToRegisterSet[IceType_v4i32] = VectorRegisters;
   TypeToRegisterSet[IceType_v4f32] = VectorRegisters;
+  TypeToRegisterSet[RegARM32::RCARM32_QtoS] = QtoSRegisters;
 
   for (size_t i = 0; i < llvm::array_lengthof(TypeToRegisterSet); ++i)
     TypeToRegisterSetUnfiltered[i] = TypeToRegisterSet[i];
 
   filterTypeToRegisterSet(
       Ctx, RegARM32::Reg_NUM, TypeToRegisterSet,
       llvm::array_lengthof(TypeToRegisterSet), [](int32_t RegNum) -> IceString {
         // This function simply removes ", " from the register name.
         IceString Name = RegARM32::getRegName(RegNum);
         constexpr const char RegSeparator[] = ", ";
@@ skipping 3469 matching lines @@
     case IceType_v4i32: {
       UnimplementedLoweringError(this, Inst);
       break;
     }
     }
     break;
   }
   }
 }
 
-void TargetARM32::lowerExtractElement(const InstExtractElement *Inst) {
-  UnimplementedLoweringError(this, Inst);
+void TargetARM32::lowerExtractElement(const InstExtractElement *Instr) {
+  Variable *Dest = Instr->getDest();
+  auto DestTy = Dest->getType();
+
+  if (Dest->isRematerializable()) {
+    Context.insert<InstFakeDef>(Dest);

[Jim Stichnoth, 2016/02/03 15:28:37]

Maybe I haven't thought this through well enough, but this just seems wrong.

[John, 2016/02/03 16:06:51]

Yup, this is wrong. you have to handle these (which are just stack 'alloca'ed
arrays.)

If I am not mistaken, legalizeToReg() below will emit code to load from memory

+    return;
+  }
+
+  Variable *Src0 = legalizeToReg(Instr->getSrc(0));

[Jim Stichnoth, 2016/02/03 15:28:38]

Optional: It would be nice if InstExtractElement had suitably-named trivial
methods to access its operands, instead of assuming a numbering.  See
InstStore::get{Addr,Data}() as an example.

+  Operand *Src1 = Instr->getSrc(1);
+
+  if (const auto *Imm = llvm::dyn_cast<ConstantInteger32>(Src1)) {
+    auto Index = Imm->getValue();
+    Variable *T = makeReg(DestTy);
+
+    if (isFloatingType(DestTy)) {
+      // We need to make sure the source is in a suitable register.
+      Src0->setRegClass(RegARM32::RCARM32_QtoS);

[Jim Stichnoth, 2016/02/03 15:28:38]

It's possible (though unlikely) that legalizeToReg(Instr->getSrc(0)) just
returns its argument without creating a new temporary, if src0 is already known
to be a pre-colored or infinite-weight variable.  It's also possible that it
returns an existing temporary from the previous instruction lowering due to the
local availability optimization.

In either of these cases, you really don't want to override Src0's register
class.

Instead, move Src0 into a new temporary with the desired register class.

[Eric Holk, 2016/02/03 21:02:22]

Done.

+    }
+
+    _extract(T, Src0, Index);
+    _mov(Dest, T);
+    return;
+  } else {
+    assert(false && "extract requires a constant index");

[Jim Stichnoth, 2016/02/03 15:28:38]

s/extract/extractelement
would make a more instantly understandable message.

[Eric Holk, 2016/02/03 21:02:21]

Done.

+  }
 }
 
 namespace {
 // Validates FCMPARM32_TABLE's declaration w.r.t. InstFcmp::FCondition ordering
 // (and naming).
 enum {
 #define X(val, CC0, CC1) _fcmp_ll_##val,
   FCMPARM32_TABLE
 #undef X
       _fcmp_ll_NUM
@@ skipping 373 matching lines @@
   _mov(T, _0);
   CondWhenTrue Cond = lowerIcmpCond(Inst);
   _mov_redefined(T, _1, Cond.WhenTrue0);
   _mov(Dest, T);
 
   assert(Cond.WhenTrue1 == CondARM32::kNone);
 
   return;
 }
 
-void TargetARM32::lowerInsertElement(const InstInsertElement *Inst) {
-  UnimplementedLoweringError(this, Inst);
+void TargetARM32::lowerInsertElement(const InstInsertElement *Instr) {
+  Variable *Dest = Instr->getDest();
+  auto DestTy = Dest->getType();
+
+  if (Dest->isRematerializable()) {
+    Context.insert<InstFakeDef>(Dest);
+    return;
+  }
+
+  Variable *Src0 = legalizeToReg(Instr->getSrc(0));
+  Variable *Src1 = legalizeToReg(Instr->getSrc(1));
+  Operand *Src2 = Instr->getSrc(2);
+
+  if (const auto *Imm = llvm::dyn_cast<ConstantInteger32>(Src2)) {
+    auto Index = Imm->getValue();
+    Variable *T = makeReg(DestTy);
+
+    if (isFloatingType(DestTy)) {
+      T->setRegClass(RegARM32::RCARM32_QtoS);
+    }
+
+    _mov(T, Src0);
+    _insert(T, Src1, Index);
+    _set_dest_redefined();
+    _mov(Dest, T);
+    return;
+  }
+  assert(false && "insert requires a constant index");
 }
 
 namespace {
 inline uint64_t getConstantMemoryOrder(Operand *Opnd) {
   if (auto *Integer = llvm::dyn_cast<ConstantInteger32>(Opnd))
     return Integer->getValue();
   return Intrinsics::MemoryOrderInvalid;
 }
 } // end of anonymous namespace
 
@@ skipping 2276 matching lines @@
   Str << ".eabi_attribute 14, 3   @ Tag_ABI_PCS_R9_use: Not used\n";
 }
 
 llvm::SmallBitVector TargetARM32::TypeToRegisterSet[RegARM32::RCARM32_NUM];
 llvm::SmallBitVector
     TargetARM32::TypeToRegisterSetUnfiltered[RegARM32::RCARM32_NUM];
 llvm::SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM];
 
 } // end of namespace ARM32
 } // end of namespace Ice