Subzero: ARM32: lowering of vector insert and extract.

src/IceRegistersARM32.h

 //===- subzero/src/IceRegistersARM32.h - Register information ---*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 201 matching lines @@
   assert(isEncodedQReg(RegNum));
   return QRegister(RegTable[RegNum].Encoding);
 }
 
 static inline IceString getRegName(int32_t RegNum) {
   assert(RegNum >= 0);
   assert(RegNum < Reg_NUM);
   return RegTable[RegNum].Name;
 }
 
 // Extend enum RegClass with ARM32-specific register classes (if any).

[Jim Stichnoth, 2016/02/03 15:28:37]

I guess the "(if any)" comment can be dropped.

[Eric Holk, 2016/02/03 21:02:21]

Done.

-enum RegClassARM32 : uint8_t { RCARM32_NUM = RC_Target };
+enum RegClassARM32 : uint8_t {
+  RCARM32_QtoS = RC_Target, // Denotes Q registers that are aliased by S
+                            // registers.
+  RCARM32_NUM
+};
 
 } // end of namespace RegARM32
 } // end of namespace ARM32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEREGISTERSARM32_H