Improve readability of error messages for VADD in ARM assembler.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 139 matching lines @@
   case IceType_i8:
   case IceType_f32:
     return 0;
   case IceType_i16:
     return 1;
   case IceType_i32:
     return 2;
   case IceType_i64:
     return 3;
   default:
-    llvm::report_fatal_error(
-        std::string("SIMD op: Don't understand element type ") +
-        typeString(ElmtTy));
+    llvm::report_fatal_error("SIMD op: Don't understand element type " +
+                             std::string(typeString(ElmtTy)));
   }
 }
 
 IValueT encodeShift(OperandARM32::ShiftKind Shift) {
   // Follows encoding in ARM section A8.4.1 "Constant shifts".
   switch (Shift) {
   case OperandARM32::kNoShift:
   case OperandARM32::LSL:
     return 0; // 0b00
   case OperandARM32::LSR:
@@ skipping 2674 matching lines @@
   constexpr const char *Vsqrts = "vsqrts";
   IValueT Sd = encodeSRegister(OpSd, "Sd", Vsqrts);
   IValueT Sm = encodeSRegister(OpSm, "Sm", Vsqrts);
   constexpr IValueT VsqrtsOpcode = B23 | B21 | B20 | B16 | B7 | B6;
   constexpr IValueT S0 = 0;
   emitVFPsss(Cond, VsqrtsOpcode, Sd, S0, Sm);
 }
 
 } // end of namespace ARM32
 } // end of namespace Ice