Implements the vector add instructions in the integrated ARM assembler.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 126 matching lines @@
 }
 
 RegARM32::GPRRegister decodeGPRRegister(IValueT R) {
   return static_cast<RegARM32::GPRRegister>(R);
 }
 
 IValueT encodeCondition(CondARM32::Cond Cond) {
   return static_cast<IValueT>(Cond);
 }
 
+// Returns the SIMD encoding of the element type for the vector.
+IValueT encodeElmtType(Type ElmtTy) {
+  switch (ElmtTy) {
+  case IceType_i8:
+  case IceType_f32:
+    return 0;
+  case IceType_i16:
+    return 1;
+  case IceType_i32:
+    return 2;
+  case IceType_i64:
+    return 3;
+  default:
+    llvm::report_fatal_error(
+        std::string("SIMD op: Don't understand element type ") +
+        typeString(ElmtTy));
+  }
+}
+
 IValueT encodeShift(OperandARM32::ShiftKind Shift) {
   // Follows encoding in ARM section A8.4.1 "Constant shifts".
   switch (Shift) {
   case OperandARM32::kNoShift:
   case OperandARM32::LSL:
     return 0; // 0b00
   case OperandARM32::LSR:
     return 1; // 0b01
   case OperandARM32::ASR:
     return 2; // 0b10
@@ skipping 27 matching lines @@
 
 IValueT getEncodedSRegNum(const Variable *Var) {
   assert(Var->hasReg());
   return RegARM32::getEncodedSReg(Var->getRegNum());
 }
 
 IValueT getEncodedDRegNum(const Variable *Var) {
   return RegARM32::getEncodedDReg(Var->getRegNum());
 }
 
+IValueT getEncodedQRegNum(const Variable *Var) {
+  return RegARM32::getEncodedQReg(Var->getRegNum());
+}
+
+IValueT mapQRegToDReg(IValueT EncodedQReg) { return EncodedQReg << 1; }
+
 IValueT getYInRegXXXXY(IValueT RegXXXXY) { return RegXXXXY & 0x1; }
 
 IValueT getXXXXInRegXXXXY(IValueT RegXXXXY) { return RegXXXXY >> 1; }
 
 IValueT getYInRegYXXXX(IValueT RegYXXXX) { return RegYXXXX >> 4; }
 
 IValueT getXXXXInRegYXXXX(IValueT RegYXXXX) { return RegYXXXX & 0x0f; }
 
 // Defines layouts of an operand representing a (register) memory address,
 // possibly modified by an immediate value.
@@ skipping 94 matching lines @@
 
 // Encodes mmmmtt01ssss for data-processing operands where mmmm=Rm, ssss=Rs, and
 // tt=Shift.
 IValueT encodeShiftRotateReg(IValueT Rm, OperandARM32::ShiftKind Shift,
                              IValueT Rs) {
   return (Rs << kRsShift) | (encodeShift(Shift) << kShiftShift) | B4 |
          (Rm << kRmShift);
 }
 
 // Defines the set of registers expected in an operand.
-enum RegSetWanted { WantGPRegs, WantSRegs, WantDRegs };
+enum RegSetWanted { WantGPRegs, WantSRegs, WantDRegs, WantQRegs };
 
 EncodedOperand encodeOperand(const Operand *Opnd, IValueT &Value,
                              RegSetWanted WantedRegSet) {
   Value = 0; // Make sure initialized.
   if (const auto *Var = llvm::dyn_cast<Variable>(Opnd)) {
     if (Var->hasReg()) {
       switch (WantedRegSet) {
       case WantGPRegs:
         Value = getEncodedGPRegNum(Var);
         break;
       case WantSRegs:
         Value = getEncodedSRegNum(Var);
         break;
       case WantDRegs:
         Value = getEncodedDRegNum(Var);
         break;
+      case WantQRegs:
+        Value = getEncodedQRegNum(Var);
+        break;
       }
       return EncodedAsRegister;
     }
     return CantEncode;
   }
   if (const auto *FlexImm = llvm::dyn_cast<OperandARM32FlexImm>(Opnd)) {
     const IValueT Immed8 = FlexImm->getImm();
     const IValueT Rotate = FlexImm->getRotateAmt();
     if (!((Rotate < (1 << kRotateBits)) && (Immed8 < (1 << kImmed8Bits))))
       return CantEncode;
@@ skipping 161 matching lines @@
 IValueT encodeSRegister(const Operand *OpReg, const char *RegName,
                         const char *InstName) {
   return encodeRegister(OpReg, WantSRegs, RegName, InstName);
 }
 
 IValueT encodeDRegister(const Operand *OpReg, const char *RegName,
                         const char *InstName) {
   return encodeRegister(OpReg, WantDRegs, RegName, InstName);
 }
 
+IValueT encodeQRegister(const Operand *OpReg, const char *RegName,
+                        const char *InstName) {
+  return encodeRegister(OpReg, WantQRegs, RegName, InstName);
+}
+
 void verifyPOrNotW(IValueT Address, const char *InstName) {
   if (BuildDefs::minimal())
     return;
   if (!isBitSet(P, Address) && isBitSet(W, Address))
     llvm::report_fatal_error(std::string(InstName) +
                              ": P=0 when W=1 not allowed");
 }
 
 void verifyRegsNotEq(IValueT Reg1, const char *Reg1Name, IValueT Reg2,
                      const char *Reg2Name, const char *InstName) {
@@ skipping 507 matching lines @@
   IValueT Rot = encodeRotation(Rotation);
   if (!Utils::IsUint(2, Rot))
     llvm::report_fatal_error(std::string(InstName) +
                              ": Illegal rotation value");
   IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | Opcode |
                      (Rn << kRnShift) | (Rd << kRdShift) |
                      (Rot << kRotationShift) | B6 | B5 | B4 | (Rm << kRmShift);
   emitInst(Encoding);
 }
 
+void AssemblerARM32::emitSIMD(IValueT Opcode, Type ElmtTy, IValueT Dd,
+                              IValueT Dn, IValueT Dm, bool UseQRegs) {
+  IValueT Sz = encodeElmtType(ElmtTy);
+  assert(Utils::IsUint(2, Sz));
+  IValueT Encoding =
+      Opcode | B25 | (encodeCondition(CondARM32::kNone) << kConditionShift) |
+      (Sz << 20) | (getYInRegYXXXX(Dd) << 22) | (getXXXXInRegYXXXX(Dn) << 16) |
+      (getXXXXInRegYXXXX(Dd) << 12) | (getYInRegYXXXX(Dn) << 7) |
+      (encodeBool(UseQRegs) << 6) | (getYInRegYXXXX(Dm) << 5) |
+      getXXXXInRegYXXXX(Dm);
+  emitInst(Encoding);
+}
+
+void AssemblerARM32::emitSIMDqqq(IValueT Opcode, Type ElmtTy,
+                                 const Operand *OpQd, const Operand *OpQn,
+                                 const Operand *OpQm, const char *OpcodeName) {
+  IValueT Qd = encodeQRegister(OpQd, "Qd", OpcodeName);
+  IValueT Qn = encodeQRegister(OpQn, "Qn", OpcodeName);
+  IValueT Qm = encodeQRegister(OpQm, "Qm", OpcodeName);
+  constexpr bool UseQRegs = true;
+  emitSIMD(Opcode, ElmtTy, mapQRegToDReg(Qd), mapQRegToDReg(Qn),
+           mapQRegToDReg(Qm), UseQRegs);
+}
+
 void AssemblerARM32::emitVFPddd(CondARM32::Cond Cond, IValueT Opcode,
                                 IValueT Dd, IValueT Dn, IValueT Dm) {
   assert(Dd < RegARM32::getNumDRegs());
   assert(Dn < RegARM32::getNumDRegs());
   assert(Dm < RegARM32::getNumDRegs());
   assert(CondARM32::isDefined(Cond));
   constexpr IValueT VFPOpcode = B27 | B26 | B25 | B11 | B9 | B8;
   const IValueT Encoding =
       Opcode | VFPOpcode | (encodeCondition(Cond) << kConditionShift) |
       (getYInRegYXXXX(Dd) << 22) | (getXXXXInRegYXXXX(Dn) << 16) |
@@ skipping 1047 matching lines @@
   // VADD (floating-point) - ARM section A8.8.283, encoding A2:
   //   vadd<c>.f32 <Sd>, <Sn>, <Sm>
   //
   // cccc11100D11nnnndddd101sN0M0mmmm where cccc=Cond, s=0, ddddD=Rd, nnnnN=Rn,
   // and mmmmM=Rm.
   constexpr const char *Vadds = "vadds";
   constexpr IValueT VaddsOpcode = B21 | B20;
   emitVFPsss(Cond, VaddsOpcode, OpSd, OpSn, OpSm, Vadds);
 }
 
+void AssemblerARM32::vaddqi(Type ElmtTy, const Operand *OpQd,
+                            const Operand *OpQm, const Operand *OpQn) {
+  // VADD (integer) - ARM section A8.8.282, encoding A1:
+  //   vadd.<dt> <Qd>, <Qn>, <Qm>
+  //
+  // 111100100Dssnnn0ddd01000NqM0mmm0 where Dddd=OpQd, Nnnn=OpQm, Mmmm=OpQm,
+  // and dt in [i8, i16, i32, i64] where ss is the index.
+  constexpr const char *Vaddqi = "vaddqi";
+  constexpr IValueT VaddqiOpcode = B11;
+  emitSIMDqqq(VaddqiOpcode, ElmtTy, OpQd, OpQm, OpQn, Vaddqi);
+}
+
+void AssemblerARM32::vaddqf(const Operand *OpQd, const Operand *OpQn,
+                            const Operand *OpQm) {
+  // VADD (floating-point) - ARM section A8.8.283, Encoding A1:
+  //   vadd.f32 <Qd>, <Qn>, <Qm>
+  //
+  // 111100100D00nnn0ddd01101N1M0mmm0 where Dddd=Qd, Nnnn=Qn, and Mmmm=Qm.
+  constexpr const char *Vaddqf = "vaddqf";
+  constexpr IValueT VaddqfOpcode = B11 | B10 | B8;
+  emitSIMDqqq(VaddqfOpcode, IceType_f32, OpQd, OpQn, OpQm, Vaddqf);
+}
+
 void AssemblerARM32::vaddd(const Operand *OpDd, const Operand *OpDn,
                            const Operand *OpDm, CondARM32::Cond Cond) {
   // VADD (floating-point) - ARM section A8.8.283, encoding A2:
   //   vadd<c>.f64 <Dd>, <Dn>, <Dm>
   //
   // cccc11100D11nnnndddd101sN0M0mmmm where cccc=Cond, s=1, Ddddd=Rd, Nnnnn=Rn,
   // and Mmmmm=Rm.
   constexpr const char *Vaddd = "vaddd";
   constexpr IValueT VadddOpcode = B21 | B20;
   emitVFPddd(Cond, VadddOpcode, OpDd, OpDn, OpDm, Vaddd);
@@ skipping 657 matching lines @@
   constexpr const char *Vsqrts = "vsqrts";
   IValueT Sd = encodeSRegister(OpSd, "Sd", Vsqrts);
   IValueT Sm = encodeSRegister(OpSm, "Sm", Vsqrts);
   constexpr IValueT VsqrtsOpcode = B23 | B21 | B20 | B16 | B7 | B6;
   constexpr IValueT S0 = 0;
   emitVFPsss(Cond, VsqrtsOpcode, Sd, S0, Sm);
 }
 
 } // end of namespace ARM32
 } // end of namespace Ice