Implements the vector add instructions in the integrated ARM assembler.

src/DartARM32/assembler_arm.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // This is forked from Dart revision df52deea9f25690eb8b66c5995da92b70f7ac1fe
 // Please update the (git) revision if we merge changes from Dart.
 // https://code.google.com/p/dart/wiki/GettingTheSource
 
 #include "vm/globals.h"  // NOLINT
 #if defined(TARGET_ARCH_ARM)
@@ skipping 1195 matching lines @@
       return 0;
     default:
       UNREACHABLE();
       break;
   }
 
   UNREACHABLE();
   return -1;
 }
 
-
+#if 0
+// Moved to ARM32::AssemblerARM32::emitSIMDqqq()
 void Assembler::EmitSIMDqqq(int32_t opcode, OperandSize size,
                             QRegister qd, QRegister qn, QRegister qm) {
   ASSERT(TargetCPUFeatures::neon_supported());
   int sz = ShiftOfOperandSize(size);
   int32_t encoding =
       (static_cast<int32_t>(kSpecialCondition) << kConditionShift) |
       B25 | B6 |
       opcode | ((sz & 0x3) * B20) |
       ((static_cast<int32_t>(qd * 2) >> 4)*B22) |
       ((static_cast<int32_t>(qn * 2) & 0xf)*B16) |
       ((static_cast<int32_t>(qd * 2) & 0xf)*B12) |
       ((static_cast<int32_t>(qn * 2) >> 4)*B7) |
       ((static_cast<int32_t>(qm * 2) >> 4)*B5) |
       (static_cast<int32_t>(qm * 2) & 0xf);
   Emit(encoding);
 }
-
+#endif
 
 void Assembler::EmitSIMDddd(int32_t opcode, OperandSize size,
                             DRegister dd, DRegister dn, DRegister dm) {
   ASSERT(TargetCPUFeatures::neon_supported());
   int sz = ShiftOfOperandSize(size);
   int32_t encoding =
       (static_cast<int32_t>(kSpecialCondition) << kConditionShift) |
       B25 |
       opcode | ((sz & 0x3) * B20) |
       ((static_cast<int32_t>(dd) >> 4)*B22) |
       ((static_cast<int32_t>(dn) & 0xf)*B16) |
       ((static_cast<int32_t>(dd) & 0xf)*B12) |
       ((static_cast<int32_t>(dn) >> 4)*B7) |
       ((static_cast<int32_t>(dm) >> 4)*B5) |
       (static_cast<int32_t>(dm) & 0xf);
   Emit(encoding);
 }
 
 
 void Assembler::vmovq(QRegister qd, QRegister qm) {
   EmitSIMDqqq(B21 | B8 | B4, kByte, qd, qm, qm);
 }
 
-
+#if 0
+// Moved to ARM32::AssemblerARM32::vaddqi().
 void Assembler::vaddqi(OperandSize sz,
                        QRegister qd, QRegister qn, QRegister qm) {
   EmitSIMDqqq(B11, sz, qd, qn, qm);
 }
 
-
+// Moved to ARM32::AssemblerARM32::vaddqf().
 void Assembler::vaddqs(QRegister qd, QRegister qn, QRegister qm) {
   EmitSIMDqqq(B11 | B10 | B8, kSWord, qd, qn, qm);
 }
-
+#endif
 
 void Assembler::vsubqi(OperandSize sz,
                        QRegister qd, QRegister qn, QRegister qm) {
   EmitSIMDqqq(B24 | B11, sz, qd, qn, qm);
 }
 
 
 void Assembler::vsubqs(QRegister qd, QRegister qn, QRegister qm) {
   EmitSIMDqqq(B21 | B11 | B10 | B8, kSWord, qd, qn, qm);
 }
@@ skipping 2409 matching lines @@
 
 
 const char* Assembler::FpuRegisterName(FpuRegister reg) {
   ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters));
   return fpu_reg_names[reg];
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM