Implements the vector add instructions in the integrated ARM assembler.

src/IceAssemblerARM32.h

 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 300 matching lines @@
 
   // Implements uxtb/uxth depending on type of OpSrc0.
   void uxt(const Operand *OpRd, const Operand *OpSrc0, CondARM32::Cond Cond);
 
   void vaddd(const Operand *OpDd, const Operand *OpDn, const Operand *OpDm,
              CondARM32::Cond Cond);
 
   void vadds(const Operand *OpSd, const Operand *OpSn, const Operand *OpSm,
              CondARM32::Cond Cond);
 
+  // Integer vector add.
+  void vaddqi(Type ElmtTy, const Operand *OpQd, const Operand *OpQm,
+              const Operand *OpQn);
+
+  // Float vector add.
+  void vaddqf(const Operand *OpQd, const Operand *OpQm, const Operand *OpQn);
+
   void vcmpd(const Operand *OpDd, const Operand *OpDm, CondARM32::Cond cond);
 
   // Second argument of compare is zero (+0.0).
   void vcmpdz(const Operand *OpDd, CondARM32::Cond cond);
 
   void vcmps(const Operand *OpSd, const Operand *OpSm, CondARM32::Cond cond);
 
   // Second argument of compare is zero (+0.0).
   void vcmpsz(const Operand *OpSd, CondARM32::Cond cond);
 
@@ skipping 254 matching lines @@
                  const OperandARM32::ShiftKind Shift, const Operand *OpRd,
                  const Operand *OpRm, const Operand *OpSrc1,
                  const bool SetFlags, const char *InstName);
 
   // Implements various forms of signed/unsigned extend value, using pattern
   // ccccxxxxxxxxnnnnddddrr000111mmmm where cccc=Cond, xxxxxxxx<<20=Opcode,
   // nnnn=Rn, dddd=Rd, rr=Rotation, and mmmm=Rm.
   void emitSignExtend(CondARM32::Cond, IValueT Opcode, const Operand *OpRd,
                       const Operand *OpSrc0, const char *InstName);
 
+  // Implements various forms of vector (SIMD) operations.  Implements pattern
+  // 111100100Dssnnnndddn0000NQM0mmmm where ss=encodeElmtType(ElmtTy), Dddd=Dd,
+  // Nnnn=Dn, Mmmm=Dm, Q=UseQRegs, and Opcode is unioned into the pattern.
+  void emitSIMD(IValueT Opcode, Type ElmtTy, IValueT Dd, IValueT Dn, IValueT Dm,
+                bool UseQRegs);
+
+  // Implements various integer forms of vector (SIMD) operations using Q
+  // registers. Implements pattern 111100100Dssnnn0ddd00000N1M0mmm0 where
+  // ss=encodeElmtType(ElmtTy), Dddd=Qd, Nnnn=Qn, Mmmm=Qm, and Opcode is unioned
+  // into the pattern.
+  void emitSIMDqqq(IValueT Opcode, Type ElmtTy, const Operand *OpQd,
+                   const Operand *OpQn, const Operand *OpQm,
+                   const char *OpcodeName);
+
   // Pattern cccctttxxxxnnnn0000iiiiiiiiiiii where cccc=Cond, nnnn=Rn,
   // ttt=Instruction type (derived from OpSrc1), iiiiiiiiiiii is derived from
   // OpSrc1, and xxxx=Opcode.
   void emitCompareOp(CondARM32::Cond Cond, IValueT Opcode, const Operand *OpRn,
                      const Operand *OpSrc1, const char *CmpName);
 
   void emitBranch(Label *L, CondARM32::Cond, bool Link);
 
   // Encodes the given Offset into the branch instruction Inst.
   IValueT encodeBranchOffset(IOffsetT Offset, IValueT Inst);
@@ skipping 21 matching lines @@
 
   void emitVFPsss(CondARM32::Cond Cond, IValueT Opcode, const Operand *OpSd,
                   const Operand *OpSn, const Operand *OpSm,
                   const char *InstName);
 };
 
 } // end of namespace ARM32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H