Add VSUB vector instruction to the integrated ARM assembler.

src/IceAssemblerARM32.cpp

Index: src/IceAssemblerARM32.cpp
diff --git a/src/IceAssemblerARM32.cpp b/src/IceAssemblerARM32.cpp
index 13e2b1a4d09f2bdba2229ae5b89c8ff1ecd6ecb1..0583813459e6a307c204be08fd358476cd21e161 100644
--- a/src/IceAssemblerARM32.cpp
+++ b/src/IceAssemblerARM32.cpp
@@ -2159,7 +2159,7 @@ void AssemblerARM32::vaddqi(Type ElmtTy, const Operand *OpQd,
   // VADD (integer) - ARM section A8.8.282, encoding A1:
   //   vadd.<dt> <Qd>, <Qn>, <Qm>
   //
-  // 111100100Dssnnn0ddd01000NqM0mmm0 where Dddd=OpQd, Nnnn=OpQm, Mmmm=OpQm,
+  // 111100100Dssnnn0ddd01000N1M0mmm0 where Dddd=OpQd, Nnnn=OpQm, Mmmm=OpQm,
   // and dt in [i8, i16, i32, i64] where ss is the index.
   constexpr const char *Vaddqi = "vaddqi";
   constexpr IValueT VaddqiOpcode = B11;
@@ -2778,6 +2778,29 @@ void AssemblerARM32::vsubd(const Operand *OpDd, const Operand *OpDn,
   emitVFPddd(Cond, VsubdOpcode, OpDd, OpDn, OpDm, Vsubd);
 }
 
+void AssemblerARM32::vsubqi(Type ElmtTy, const Operand *OpQd,
+                            const Operand *OpQm, const Operand *OpQn) {
+  // VSUB (integer) - ARM section A8.8.414, encoding A1:
+  //   vsub.<dt> <Qd>, <Qn>, <Qm>
+  //
+  // 111100110Dssnnn0ddd01000N1M0mmm0 where Dddd=OpQd, Nnnn=OpQm, Mmmm=OpQm,
+  // and dt in [i8, i16, i32, i64] where ss is the index.
+  constexpr const char *Vsubqi = "vsubqi";
+  constexpr IValueT VsubqiOpcode = B24 | B11;
+  emitSIMDqqq(VsubqiOpcode, ElmtTy, OpQd, OpQm, OpQn, Vsubqi);
+}
+
+void AssemblerARM32::vsubqf(const Operand *OpQd, const Operand *OpQn,
+                            const Operand *OpQm) {
+  // VSUB (floating-point) - ARM section A8.8.415, Encoding A1:
+  //   vsub.f32 <Qd>, <Qn>, <Qm>
+  //
+  // 111100100D10nnn0ddd01101N1M0mmm0 where Dddd=Qd, Nnnn=Qn, and Mmmm=Qm.
+  constexpr const char *Vsubqf = "vsubqf";
+  constexpr IValueT VsubqfOpcode = B21 | B11 | B10 | B8;
+  emitSIMDqqq(VsubqfOpcode, IceType_f32, OpQd, OpQn, OpQm, Vsubqf);
+}
+
 void AssemblerARM32::emitVStackOp(CondARM32::Cond Cond, IValueT Opcode,
                                   const Variable *OpBaseReg,
                                   SizeT NumConsecRegs) {