Add vmov between integers and floats in ARM assembler.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 2409 matching lines @@
   //
   // cccc11101D110000dddd101101M0mmmm where cccc=Cond, Ddddd=Sd, and Mmmmm=Sm.
   constexpr const char *Vmovdd = "Vmovdd";
   IValueT Dd = encodeSRegister(OpDd, "Dd", Vmovdd);
   IValueT Dm = encodeSRegister(OpDm, "Dm", Vmovdd);
   constexpr IValueT VmovddOpcode = B23 | B21 | B20 | B6;
   constexpr IValueT D0 = 0;
   emitVFPddd(Cond, VmovddOpcode, Dd, D0, Dm);
 }
 
+void AssemblerARM32::vmovrs(const Operand *OpRt, const Operand *OpSn,
+                            CondARM32::Cond Cond) {
+  // VMOV (between ARM core register and single-precision register)
+  //   ARM section A8.8.343, encoding A1.
+  //
+  //   vmov<c> <Rt>, <Sn>
+  //
+  // cccc11100001nnnntttt1010N0010000 where cccc=Cond, nnnnN = Sn, and tttt=Rt.
+  constexpr const char *Vmovrs = "vmovrs";
+  IValueT Rt = encodeGPRegister(OpRt, "Rt", Vmovrs);
+  IValueT Sn = encodeSRegister(OpSn, "Sn", Vmovrs);
+  assert(CondARM32::isDefined(Cond));
+  IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | B27 | B26 |
+                     B25 | B20 | B11 | B9 | B4 | (getXXXXInRegXXXXY(Sn) << 16) |
+                     (Rt << kRdShift) | (getYInRegXXXXY(Sn) << 7);
+  emitInst(Encoding);
+}
+
 void AssemblerARM32::vmovs(const Operand *OpSd,
                            const OperandARM32FlexFpImm *OpFpImm,
                            CondARM32::Cond Cond) {
   // VMOV (immediate) - ARM section A8.8.339, encoding A2:
   //   vmov<c>.f32 <Sd>, #<imm>
   //
   // cccc11101D11xxxxdddd10100000yyyy where cccc=Cond, ddddD=Sn, xxxxyyyy=imm.
   constexpr const char *Vmovs = "vmovs";
   IValueT Sd = encodeSRegister(OpSd, "Sd", Vmovs);
   IValueT Imm8 = OpFpImm->getModifiedImm();
@@ skipping 18 matching lines @@
   emitVFPsss(Cond, VmovssOpcode, Sd, S0, Sm);
 }
 
 void AssemblerARM32::vmovsr(const Operand *OpSn, const Operand *OpRt,
                             CondARM32::Cond Cond) {
   // VMOV (between ARM core register and single-precision register)
   //   ARM section A8.8.343, encoding A1.
   //
   //   vmov<c> <Sn>, <Rt>
   //
-  // cccc1110000onnnntttt1010N0010000 where cccc=Cond, nnnnN = Sn, and tttt=Rt.
+  // cccc11100000nnnntttt1010N0010000 where cccc=Cond, nnnnN = Sn, and tttt=Rt.
   constexpr const char *Vmovsr = "vmovsr";
   IValueT Sn = encodeSRegister(OpSn, "Sn", Vmovsr);
   IValueT Rt = encodeGPRegister(OpRt, "Rt", Vmovsr);
   assert(Sn < RegARM32::getNumSRegs());
   assert(Rt < RegARM32::getNumGPRegs());
   assert(CondARM32::isDefined(Cond));
   IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | B27 | B26 |
                      B25 | B11 | B9 | B4 | (getXXXXInRegXXXXY(Sn) << 16) |
                      (Rt << kRdShift) | (getYInRegXXXXY(Sn) << 7);
   emitInst(Encoding);
@@ skipping 168 matching lines @@
   //
   // cccc11010D101101dddd1010iiiiiiii where cccc=Cond, ddddD=BaseReg, and
   // iiiiiiii=NumConsecRegs.
   constexpr IValueT VpushOpcode =
       B27 | B26 | B24 | B21 | B19 | B18 | B16 | B11 | B9;
   emitVStackOp(Cond, VpushOpcode, OpBaseReg, NumConsecRegs);
 }
 
 } // end of namespace ARM32
 } // end of namespace Ice