Add VSQRT instruction to the integrated ARM assembler.

src/IceInstARM32.cpp

 //===- subzero/src/IceInstARM32.cpp - ARM32 instruction implementation ----===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 79 matching lines @@
 
 void InstARM32::startNextInst(const Cfg *Func) const {
   if (auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>())
     Asm->incEmitTextSize(InstSize);
 }
 
 void InstARM32::emitUsingTextFixup(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   GlobalContext *Ctx = Func->getContext();
-  if (Ctx->getFlags().getDisableHybridAssembly()) {
-    UnimplementedError(Ctx->getFlags());
-    return;
-  }
   auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
   std::string Buffer;
   llvm::raw_string_ostream StrBuf(Buffer);
   OstreamLocker L(Ctx);
   Ostream &OldStr = Ctx->getStrEmit();
   Ctx->setStrEmit(StrBuf);
   // Start counting instructions here, so that emit() methods don't
   // need to call this for the first instruction.
   Asm->resetEmitTextSize();
   Asm->incEmitTextSize(InstSize);
   emit(Func);
   Ctx->setStrEmit(OldStr);
+  if (Ctx->getFlags().getDisableHybridAssembly()) {
+    llvm::errs() << "Can't assemble: " << StrBuf.str() << "\n";
+    UnimplementedError(Ctx->getFlags());
+    return;
+  }
   Asm->emitTextInst(StrBuf.str(), Asm->getEmitTextSize());
 }
 
 void InstARM32::emitIAS(const Cfg *Func) const { emitUsingTextFixup(Func); }
 
 void InstARM32Pred::emitUnaryopGPR(const char *Opcode,
                                    const InstARM32Pred *Inst, const Cfg *Func,
                                    bool NeedsWidthSuffix) {
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(Inst->getSrcSize() == 1);
@@ skipping 1550 matching lines @@
 }
 
 template <> void InstARM32Uxt::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 1);
   auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
   Asm->uxt(getDest(), getSrc(0), getPredicate());
   if (Asm->needsTextFixup())
     emitUsingTextFixup(Func);
 }
 
+template <InstARM32::InstKindARM32 K>
+void InstARM32UnaryopFP<K>::emitIAS(const Cfg *Func) const {
+  emitUsingTextFixup(Func);
+}
+
+template <> void InstARM32Vsqrt::emitIAS(const Cfg *Func) const {
+  assert(getSrcSize() == 1);
+  auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
+  const Operand *Dest = getDest();
+  switch (Dest->getType()) {
+  case IceType_f32:
+    Asm->vsqrts(Dest, getSrc(0), getPredicate());
+    break;
+  case IceType_f64:
+    Asm->vsqrtd(Dest, getSrc(0), getPredicate());
+    break;
+  default:
+    llvm::report_fatal_error("Vqrt of non-floating type");

[Jim Stichnoth, 2016/01/29 20:48:02]

Vsqrt

[Karl, 2016/01/29 22:00:55]

Done.

+  }
+  if (Asm->needsTextFixup())
+    emitUsingTextFixup(Func);
+}
+
 const char *InstARM32Pop::getGPROpcode() const { return "pop"; }
 
 const char *InstARM32Pop::getSRegOpcode() const { return "vpop"; }
 
 Variable *InstARM32Pop::getStackReg(SizeT Index) const { return Dests[Index]; }
 
 SizeT InstARM32Pop::getNumStackRegs() const { return Dests.size(); }
 
 void InstARM32Pop::emitSingleGPR(const Cfg *Func, const EmitForm Form,
                                  const Variable *Reg) const {
@@ skipping 730 matching lines @@
 
 template class InstARM32FourAddrGPR<InstARM32::Mla>;
 template class InstARM32FourAddrGPR<InstARM32::Mls>;
 
 template class InstARM32CmpLike<InstARM32::Cmn>;
 template class InstARM32CmpLike<InstARM32::Cmp>;
 template class InstARM32CmpLike<InstARM32::Tst>;
 
 } // end of namespace ARM32
 } // end of namespace Ice