Add VSQRT instruction to the integrated ARM assembler.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 2726 matching lines @@
   // VPUSH - ARM section A8.8.368, encoding A2:
   //   vpush<c> <RegList>
   //
   // cccc11010D101101dddd1010iiiiiiii where cccc=Cond, ddddD=BaseReg, and
   // iiiiiiii=NumConsecRegs.
   constexpr IValueT VpushOpcode =
       B27 | B26 | B24 | B21 | B19 | B18 | B16 | B11 | B9;
   emitVStackOp(Cond, VpushOpcode, OpBaseReg, NumConsecRegs);
 }
 
+void AssemblerARM32::vsqrtd(const Operand *OpDd, const Operand *OpDm,
+                            CondARM32::Cond Cond) {
+  // VSQRT - ARM section A8.8.401, encoding A1:
+  //   vsqrt<c>.f64 <Dd>, <Dm>
+  //
+  // cccc11101D110001dddd101111M0mmmm where cccc=Cond, Ddddd=Sd, and Mmmmm=Sm.
+  constexpr const char *Vsqrtd = "vsqrtd";
+  IValueT Dd = encodeDRegister(OpDd, "Dd", Vsqrtd);
+  IValueT Dm = encodeDRegister(OpDm, "Dm", Vsqrtd);
+  constexpr IValueT VsqrtdOpcode = B23 | B21 | B20 | B16 | B7 | B6;
+  constexpr IValueT D0 = 0;
+  emitVFPddd(Cond, VsqrtdOpcode, Dd, D0, Dm);
+}
+
+void AssemblerARM32::vsqrts(const Operand *OpSd, const Operand *OpSm,
+                            CondARM32::Cond Cond) {
+  // VSQRT - ARM section A8.8.401, encoding A1:
+  //   vsqrt<c>.f32 <Sd>, <Sm>
+  //
+  // cccc11101D110001dddd101011M0mmmm where cccc=Cond, ddddD=Sd, and mmmmM=Sm.
+  constexpr const char *Vsqrts = "vsqrts";
+  IValueT Sd = encodeSRegister(OpSd, "Sd", Vsqrts);
+  IValueT Sm = encodeSRegister(OpSm, "Sm", Vsqrts);
+  constexpr IValueT VsqrtsOpcode = B23 | B21 | B20 | B16 | B7 | B6;
+  constexpr IValueT S0 = 0;
+  emitVFPsss(Cond, VsqrtsOpcode, Sd, S0, Sm);
+}
+
 } // end of namespace ARM32
 } // end of namespace Ice