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1 | 1 |
2 // Copyright 2012 the V8 project authors. All rights reserved. | 2 // Copyright 2012 the V8 project authors. All rights reserved. |
3 // Use of this source code is governed by a BSD-style license that can be | 3 // Use of this source code is governed by a BSD-style license that can be |
4 // found in the LICENSE file. | 4 // found in the LICENSE file. |
5 | 5 |
6 #include <limits.h> // For LONG_MIN, LONG_MAX. | 6 #include <limits.h> // For LONG_MIN, LONG_MAX. |
7 | 7 |
8 #if V8_TARGET_ARCH_MIPS | 8 #if V8_TARGET_ARCH_MIPS |
9 | 9 |
10 #include "src/base/bits.h" | 10 #include "src/base/bits.h" |
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1389 // Simple conversion. | 1389 // Simple conversion. |
1390 bind(&simple_convert); | 1390 bind(&simple_convert); |
1391 trunc_w_d(scratch, fd); | 1391 trunc_w_d(scratch, fd); |
1392 mfc1(rs, scratch); | 1392 mfc1(rs, scratch); |
1393 | 1393 |
1394 bind(&done); | 1394 bind(&done); |
1395 } | 1395 } |
1396 | 1396 |
1397 | 1397 |
1398 void MacroAssembler::Mthc1(Register rt, FPURegister fs) { | 1398 void MacroAssembler::Mthc1(Register rt, FPURegister fs) { |
1399 if (IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) { | 1399 if (IsFp64Mode()) { |
1400 mthc1(rt, fs); | 1400 mthc1(rt, fs); |
1401 } else { | 1401 } else { |
1402 mtc1(rt, fs.high()); | 1402 mtc1(rt, fs.high()); |
1403 } | 1403 } |
1404 } | 1404 } |
1405 | 1405 |
1406 | 1406 |
1407 void MacroAssembler::Mfhc1(Register rt, FPURegister fs) { | 1407 void MacroAssembler::Mfhc1(Register rt, FPURegister fs) { |
1408 if (IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) { | 1408 if (IsFp64Mode()) { |
1409 mfhc1(rt, fs); | 1409 mfhc1(rt, fs); |
1410 } else { | 1410 } else { |
1411 mfc1(rt, fs.high()); | 1411 mfc1(rt, fs.high()); |
1412 } | 1412 } |
1413 } | 1413 } |
1414 | 1414 |
1415 | 1415 |
1416 void MacroAssembler::BranchFCommon(SecondaryField sizeField, Label* target, | 1416 void MacroAssembler::BranchFCommon(SecondaryField sizeField, Label* target, |
1417 Label* nan, Condition cond, FPURegister cmp1, | 1417 Label* nan, Condition cond, FPURegister cmp1, |
1418 FPURegister cmp2, BranchDelaySlot bd) { | 1418 FPURegister cmp2, BranchDelaySlot bd) { |
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5768 if (mag.shift > 0) sra(result, result, mag.shift); | 5768 if (mag.shift > 0) sra(result, result, mag.shift); |
5769 srl(at, dividend, 31); | 5769 srl(at, dividend, 31); |
5770 Addu(result, result, Operand(at)); | 5770 Addu(result, result, Operand(at)); |
5771 } | 5771 } |
5772 | 5772 |
5773 | 5773 |
5774 } // namespace internal | 5774 } // namespace internal |
5775 } // namespace v8 | 5775 } // namespace v8 |
5776 | 5776 |
5777 #endif // V8_TARGET_ARCH_MIPS | 5777 #endif // V8_TARGET_ARCH_MIPS |
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