Add vmov between floating point registers to ARM assembler.

tests_lit/assembler/arm32/vmov-fp.ll

Index: tests_lit/assembler/arm32/vmov-fp.ll
diff --git a/tests_lit/assembler/arm32/vadd.ll b/tests_lit/assembler/arm32/vmov-fp.ll
similarity index 52%
copy from tests_lit/assembler/arm32/vadd.ll
copy to tests_lit/assembler/arm32/vmov-fp.ll
index b219a71e4a4d12471936f5f08f4358478245ad4a..277632a5c7c6ec6011a2f4fdd3d7702a550f0af3 100644
--- a/tests_lit/assembler/arm32/vadd.ll
+++ b/tests_lit/assembler/arm32/vmov-fp.ll
@@ -1,7 +1,8 @@
-; Show that we know how to translate vadd.
+; Show that we know how to move between floating point registers.
 
-; NOTE: Restricts S and D registers to ones that will better test S/D
-; register encodings.
+; NOTE: We use the select instruction to fire this in -Om1, since a
+; vmovne is generated (after a branch) to (conditionally) assign the
+; else value.
 
 ; REQUIRES: allow_dump
 
@@ -27,32 +28,30 @@
 ; RUN:   -reg-use s20,s22,d20,d22 \
 ; RUN:   | FileCheck %s --check-prefix=DIS
 
-define internal float @testVaddFloat(float %v1, float %v2) {
-; ASM-LABEL: testVaddFloat:
-; DIS-LABEL: 00000000 <testVaddFloat>:
-; IASM-LABEL: testVaddFloat:
+define internal float @moveFloat() {
+; ASM-LABEL: moveFloat:
+; DIS-LABEL: 00000000 <moveFloat>:
+; IASM-LABEL: moveFloat:
 
-entry:
-  %res = fadd float %v1, %v2
+  %v = select i1 true, float 0.5, float 1.5
 
-; ASM:     vadd.f32        s20, s20, s22
-; DIS:   1c:       ee3aaa0b
-; IASM-NOT:     vadd
+; ASM:  vmovne.f32      s20, s22
+; DIS:   1c:    1eb0aa4b
+; IASM-NOT: vmovnew.f32
 
-  ret float %res
+  ret float %v
 }
 
-define internal double @testVaddDouble(double %v1, double %v2) {
-; ASM-LABEL: testVaddDouble:
-; DIS-LABEL: 00000040 <testVaddDouble>:
-; IASM-LABEL: .LtestVaddDouble$entry:
+define internal double @moveDouble() {
+; ASM-LABEL: moveDouble:
+; DIS-LABEL: 00000040 <moveDouble>:
+; IASM-LABEL: moveDouble:
 
-entry:
-  %res = fadd double %v1, %v2
+  %v = select i1 true, double 0.5, double 1.5
 
-; ASM:        vadd.f64        d20, d20, d22
-; DIS:      54:       ee744ba6
-; IASM-NOT:   vadd
+; ASM:  vmovne.f64      d20, d22
+; DIS:   54:    1ef04b66
+; IASM-NOT: vmovne.f64
 
-  ret double %res
+  ret double %v
 }