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Side by Side Diff: tests_lit/assembler/arm32/vmov-fp.ll

Issue 1645683003: Add vmov between floating point registers to ARM assembler. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Fix nits. Created 4 years, 10 months ago
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1 ; Show that we know how to translate vadd. 1 ; Show that we know how to move between floating point registers.
2 2
3 ; NOTE: Restricts S and D registers to ones that will better test S/D 3 ; NOTE: We use the select instruction to fire this in -Om1, since a
4 ; register encodings. 4 ; vmovne is generated (after a branch) to (conditionally) assign the
5 ; else value.
5 6
6 ; REQUIRES: allow_dump 7 ; REQUIRES: allow_dump
7 8
8 ; Compile using standalone assembler. 9 ; Compile using standalone assembler.
9 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \ 10 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \
10 ; RUN: -reg-use s20,s22,d20,d22 \ 11 ; RUN: -reg-use s20,s22,d20,d22 \
11 ; RUN: | FileCheck %s --check-prefix=ASM 12 ; RUN: | FileCheck %s --check-prefix=ASM
12 13
13 ; Show bytes in assembled standalone code. 14 ; Show bytes in assembled standalone code.
14 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \ 15 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
15 ; RUN: --args -Om1 \ 16 ; RUN: --args -Om1 \
16 ; RUN: -reg-use s20,s22,d20,d22 \ 17 ; RUN: -reg-use s20,s22,d20,d22 \
17 ; RUN: | FileCheck %s --check-prefix=DIS 18 ; RUN: | FileCheck %s --check-prefix=DIS
18 19
19 ; Compile using integrated assembler. 20 ; Compile using integrated assembler.
20 ; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -Om1 \ 21 ; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -Om1 \
21 ; RUN: -reg-use s20,s22,d20,d22 \ 22 ; RUN: -reg-use s20,s22,d20,d22 \
22 ; RUN: | FileCheck %s --check-prefix=IASM 23 ; RUN: | FileCheck %s --check-prefix=IASM
23 24
24 ; Show bytes in assembled integrated code. 25 ; Show bytes in assembled integrated code.
25 ; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \ 26 ; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
26 ; RUN: --args -Om1 \ 27 ; RUN: --args -Om1 \
27 ; RUN: -reg-use s20,s22,d20,d22 \ 28 ; RUN: -reg-use s20,s22,d20,d22 \
28 ; RUN: | FileCheck %s --check-prefix=DIS 29 ; RUN: | FileCheck %s --check-prefix=DIS
29 30
30 define internal float @testVaddFloat(float %v1, float %v2) { 31 define internal float @moveFloat() {
31 ; ASM-LABEL: testVaddFloat: 32 ; ASM-LABEL: moveFloat:
32 ; DIS-LABEL: 00000000 <testVaddFloat>: 33 ; DIS-LABEL: 00000000 <moveFloat>:
33 ; IASM-LABEL: testVaddFloat: 34 ; IASM-LABEL: moveFloat:
34 35
35 entry: 36 %v = select i1 true, float 0.5, float 1.5
36 %res = fadd float %v1, %v2
37 37
38 ; ASM: vadd.f32 s20, s20, s22 38 ; ASM: vmovne.f32 s20, s22
39 ; DIS: 1c: ee3aaa0b 39 ; DIS: 1c: 1eb0aa4b
40 ; IASM-NOT: vadd 40 ; IASM-NOT: vmovnew.f32
41 41
42 ret float %res 42 ret float %v
43 } 43 }
44 44
45 define internal double @testVaddDouble(double %v1, double %v2) { 45 define internal double @moveDouble() {
46 ; ASM-LABEL: testVaddDouble: 46 ; ASM-LABEL: moveDouble:
47 ; DIS-LABEL: 00000040 <testVaddDouble>: 47 ; DIS-LABEL: 00000040 <moveDouble>:
48 ; IASM-LABEL: .LtestVaddDouble$entry: 48 ; IASM-LABEL: moveDouble:
49 49
50 entry: 50 %v = select i1 true, double 0.5, double 1.5
51 %res = fadd double %v1, %v2
52 51
53 ; ASM: vadd.f64 d20, d20, d22 52 ; ASM: vmovne.f64 d20, d22
54 ; DIS: 54: ee744ba6 53 ; DIS: 54: 1ef04b66
55 ; IASM-NOT: vadd 54 ; IASM-NOT: vmovne.f64
56 55
57 ret double %res 56 ret double %v
58 } 57 }
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