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| 1 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===// | 1 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===// |
| 2 // | 2 // |
| 3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file | 3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file |
| 4 // for details. All rights reserved. Use of this source code is governed by a | 4 // for details. All rights reserved. Use of this source code is governed by a |
| 5 // BSD-style license that can be found in the LICENSE file. | 5 // BSD-style license that can be found in the LICENSE file. |
| 6 // | 6 // |
| 7 // Modified by the Subzero authors. | 7 // Modified by the Subzero authors. |
| 8 // | 8 // |
| 9 //===----------------------------------------------------------------------===// | 9 //===----------------------------------------------------------------------===// |
| 10 // | 10 // |
| (...skipping 367 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 378 | 378 |
| 379 void vldrs(const Operand *OpSd, const Operand *OpAddress, | 379 void vldrs(const Operand *OpSd, const Operand *OpAddress, |
| 380 CondARM32::Cond Cond, const TargetLowering *Lowering) { | 380 CondARM32::Cond Cond, const TargetLowering *Lowering) { |
| 381 const TargetInfo TInfo(Lowering); | 381 const TargetInfo TInfo(Lowering); |
| 382 vldrs(OpSd, OpAddress, Cond, TInfo); | 382 vldrs(OpSd, OpAddress, Cond, TInfo); |
| 383 } | 383 } |
| 384 | 384 |
| 385 void vmovd(const Operand *OpDn, const OperandARM32FlexFpImm *OpFpImm, | 385 void vmovd(const Operand *OpDn, const OperandARM32FlexFpImm *OpFpImm, |
| 386 CondARM32::Cond Cond); | 386 CondARM32::Cond Cond); |
| 387 | 387 |
| 388 void vmovdd(const Operand *OpDd, const Operand *OpDm, CondARM32::Cond Cond); |
| 389 |
| 388 void vmovs(const Operand *OpSn, const OperandARM32FlexFpImm *OpFpImm, | 390 void vmovs(const Operand *OpSn, const OperandARM32FlexFpImm *OpFpImm, |
| 389 CondARM32::Cond Cond); | 391 CondARM32::Cond Cond); |
| 390 | 392 |
| 393 void vmovss(const Operand *OpDd, const Operand *OpDm, CondARM32::Cond Cond); |
| 394 |
| 391 void vmovsr(const Operand *OpSn, const Operand *OpRt, CondARM32::Cond Cond); | 395 void vmovsr(const Operand *OpSn, const Operand *OpRt, CondARM32::Cond Cond); |
| 392 | 396 |
| 393 void vmlad(const Operand *OpDd, const Operand *OpDn, const Operand *OpDm, | 397 void vmlad(const Operand *OpDd, const Operand *OpDn, const Operand *OpDm, |
| 394 CondARM32::Cond Cond); | 398 CondARM32::Cond Cond); |
| 395 | 399 |
| 396 void vmlas(const Operand *OpSd, const Operand *OpSn, const Operand *OpSm, | 400 void vmlas(const Operand *OpSd, const Operand *OpSn, const Operand *OpSm, |
| 397 CondARM32::Cond Cond); | 401 CondARM32::Cond Cond); |
| 398 | 402 |
| 399 // Uses APSR_nzcv as register | 403 // Uses APSR_nzcv as register |
| 400 void vmrsAPSR_nzcv(CondARM32::Cond Cond); | 404 void vmrsAPSR_nzcv(CondARM32::Cond Cond); |
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| 604 | 608 |
| 605 void emitVFPsss(CondARM32::Cond Cond, IValueT Opcode, const Operand *OpSd, | 609 void emitVFPsss(CondARM32::Cond Cond, IValueT Opcode, const Operand *OpSd, |
| 606 const Operand *OpSn, const Operand *OpSm, | 610 const Operand *OpSn, const Operand *OpSm, |
| 607 const char *InstName); | 611 const char *InstName); |
| 608 }; | 612 }; |
| 609 | 613 |
| 610 } // end of namespace ARM32 | 614 } // end of namespace ARM32 |
| 611 } // end of namespace Ice | 615 } // end of namespace Ice |
| 612 | 616 |
| 613 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H | 617 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H |
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