Add vmov between floating point registers to ARM assembler.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 2395 matching lines @@
   constexpr const char *Vmovd = "vmovd";
   IValueT Dd = encodeSRegister(OpDd, "Dd", Vmovd);
   IValueT Imm8 = OpFpImm->getModifiedImm();
   assert(Imm8 < (1 << 8));
   constexpr IValueT VmovsOpcode = B23 | B21 | B20 | B8;
   IValueT OpcodePlusImm8 = VmovsOpcode | ((Imm8 >> 4) << 16) | (Imm8 & 0xf);
   constexpr IValueT D0 = 0;
   emitVFPddd(Cond, OpcodePlusImm8, Dd, D0, D0);
 }
 
+void AssemblerARM32::vmovdd(const Operand *OpDd, const Operand *OpDm,
+                            CondARM32::Cond Cond) {
+  // VMOV (register) - ARM section A8.8.340, encoding A2:
+  //   vmov<c>.f64 <Dd>, <Sm>
+  //
+  // cccc11101D110000dddd101101M0mmmm where cccc=Cond, Ddddd=Sd, and Mmmmm=Sm.
+  constexpr const char *Vmovdd = "Vmovdd";
+  IValueT Dd = encodeSRegister(OpDd, "Dd", Vmovdd);
+  IValueT Dm = encodeSRegister(OpDm, "Dm", Vmovdd);
+  constexpr IValueT VmovddOpcode = B23 | B21 | B20 | B6;
+  constexpr IValueT D0 = 0;
+  emitVFPddd(Cond, VmovddOpcode, Dd, D0, Dm);
+}
+
 void AssemblerARM32::vmovs(const Operand *OpSd,
                            const OperandARM32FlexFpImm *OpFpImm,
                            CondARM32::Cond Cond) {
   // VMOV (immediate) - ARM section A8.8.339, encoding A2:
   //   vmov<c>.f32 <Sd>, #<imm>
   //
   // cccc11101D11xxxxdddd10100000yyyy where cccc=Cond, ddddD=Sn, xxxxyyyy=imm.
   constexpr const char *Vmovs = "vmovs";
   IValueT Sd = encodeSRegister(OpSd, "Sd", Vmovs);
   IValueT Imm8 = OpFpImm->getModifiedImm();
   assert(Imm8 < (1 << 8));
   constexpr IValueT VmovsOpcode = B23 | B21 | B20;
   IValueT OpcodePlusImm8 = VmovsOpcode | ((Imm8 >> 4) << 16) | (Imm8 & 0xf);
   constexpr IValueT S0 = 0;
   emitVFPsss(Cond, OpcodePlusImm8, Sd, S0, S0);
 }
 
+void AssemblerARM32::vmovss(const Operand *OpSd, const Operand *OpSm,
+                            CondARM32::Cond Cond) {
+  // VMOV (register) - ARM section A8.8.340, encoding A2:
+  //   vmov<c>.f32 <Sd>, <Sm>
+  //
+  // cccc11101D110000dddd101001M0mmmm where cccc=Cond, ddddD=Sd, and mmmmM=Sm.
+  constexpr const char *Vmovss = "Vmovss";
+  IValueT Sd = encodeSRegister(OpSd, "Sd", Vmovss);
+  IValueT Sm = encodeSRegister(OpSm, "Sm", Vmovss);
+  constexpr IValueT VmovssOpcode = B23 | B21 | B20 | B6;
+  constexpr IValueT S0 = 0;
+  emitVFPsss(Cond, VmovssOpcode, Sd, S0, Sm);
+}
+
 void AssemblerARM32::vmovsr(const Operand *OpSn, const Operand *OpRt,
                             CondARM32::Cond Cond) {
   // VMOV (between ARM core register and single-precision register)
   //   ARM section A8.8.343, encoding A1.
   //
   //   vmov<c> <Sn>, <Rt>
   //
   // cccc1110000onnnntttt1010N0010000 where cccc=Cond, nnnnN = Sn, and tttt=Rt.
   constexpr const char *Vmovsr = "vmovsr";
   IValueT Sn = encodeSRegister(OpSn, "Sn", Vmovsr);
@@ skipping 176 matching lines @@
   //
   // cccc11010D101101dddd1010iiiiiiii where cccc=Cond, ddddD=BaseReg, and
   // iiiiiiii=NumConsecRegs.
   constexpr IValueT VpushOpcode =
       B27 | B26 | B24 | B21 | B19 | B18 | B16 | B11 | B9;
   emitVStackOp(Cond, VpushOpcode, OpBaseReg, NumConsecRegs);
 }
 
 } // end of namespace ARM32
 } // end of namespace Ice