Add the VMLS instruction to the integrated ARM assembler.

tests_lit/assembler/arm32/vmls.ll

Index: tests_lit/assembler/arm32/vmls.ll
diff --git a/tests_lit/assembler/arm32/vmla.ll b/tests_lit/assembler/arm32/vmls.ll
similarity index 57%
copy from tests_lit/assembler/arm32/vmla.ll
copy to tests_lit/assembler/arm32/vmls.ll
index 04797eea575bfd87772d21e1e1ff6d0dff2ac991..d1243cc4986ca6f44fa93b8a5d727abd32384d73 100644
--- a/tests_lit/assembler/arm32/vmla.ll
+++ b/tests_lit/assembler/arm32/vmls.ll
@@ -1,9 +1,9 @@
-; Show that we can take advantage of the vmla instruction for floating point
+; Show that we can take advantage of the vmls instruction for floating point
 ; operations during optimization.
 
-; Note that we use -O2 to force the result of the fmul to be (immediately)
-; available for the fadd. When using -Om1, the merge of fmul and fadd does not
-; happen due to intervening register spill code.
+; Note that we use -O2 to force the result of the fmul to be
+; (immediately) available for the fsub. When using -Om1, the merge of
+; fmul and fsub does not happen.
 
 ; REQUIRES: allow_dump
 
@@ -27,30 +27,30 @@
 ; RUN:   --args -O2 -reg-use=s20,s21,s22,d20,d21,d22 \
 ; RUN:   | FileCheck %s --check-prefix=DIS
 
-define internal float @mulAddFloat(float %f1, float %f2) {
-; ASM-LABEL: mulAddFloat:
-; DIS-LABEL: 00000000 <mulAddFloat>:
+define internal float @mulSubFloat(float %f1, float %f2) {
+; ASM-LABEL: mulSubFloat:
+; DIS-LABEL: 00000000 <mulSubFloat>:
 
   %v1 = fmul float %f1, 1.5
-  %v2 = fadd float %f2, %v1
+  %v2 = fsub float %f2, %v1
 
-; ASM:  vmla.f32        s21, s20, s22
-; DIS:   10:    ee4aaa0b
-; IASM-NOT: vmla
+; ASM:  vmls.f32        s21, s20, s22
+; DIS:   10:    ee4aaa4b
+; IASM-NOT: vmls.f32
 
   ret float %v2
 }
 
-define internal double @mulAddDouble(double %f1, double %f2) {
-; ASM-LABEL: mulAddDouble:
-; DIS-LABEL: 00000020 <mulAddDouble>:
+define internal double @mulSubDouble(double %f1, double %f2) {
+; ASM-LABEL: mulSubDouble:
+; DIS-LABEL: 00000020 <mulSubDouble>:
 
   %v1 = fmul double %f1, 1.5
-  %v2 = fadd double %f2, %v1
+  %v2 = fsub double %f2, %v1
 
-; ASM:  vmla.f64        d21, d20, d22
-; DIS:   2c:    ee445ba6
-; IASM-NOT: vmla
+; ASM:  vmls.f64        d21, d20, d22
+; DIS:   2c:    ee445be6
+; IASM-NOT: vmls.f64
 
   ret double %v2
 }