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Side by Side Diff: src/IceAssemblerARM32.h

Issue 1642303002: Add the VMLS instruction to the integrated ARM assembler. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Fix comment in test. Created 4 years, 10 months ago
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1 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===// 1 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===//
2 // 2 //
3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
4 // for details. All rights reserved. Use of this source code is governed by a 4 // for details. All rights reserved. Use of this source code is governed by a
5 // BSD-style license that can be found in the LICENSE file. 5 // BSD-style license that can be found in the LICENSE file.
6 // 6 //
7 // Modified by the Subzero authors. 7 // Modified by the Subzero authors.
8 // 8 //
9 //===----------------------------------------------------------------------===// 9 //===----------------------------------------------------------------------===//
10 // 10 //
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395 void vmovss(const Operand *OpDd, const Variable *OpDm, CondARM32::Cond Cond); 395 void vmovss(const Operand *OpDd, const Variable *OpDm, CondARM32::Cond Cond);
396 396
397 void vmovsr(const Operand *OpSn, const Operand *OpRt, CondARM32::Cond Cond); 397 void vmovsr(const Operand *OpSn, const Operand *OpRt, CondARM32::Cond Cond);
398 398
399 void vmlad(const Operand *OpDd, const Operand *OpDn, const Operand *OpDm, 399 void vmlad(const Operand *OpDd, const Operand *OpDn, const Operand *OpDm,
400 CondARM32::Cond Cond); 400 CondARM32::Cond Cond);
401 401
402 void vmlas(const Operand *OpSd, const Operand *OpSn, const Operand *OpSm, 402 void vmlas(const Operand *OpSd, const Operand *OpSn, const Operand *OpSm,
403 CondARM32::Cond Cond); 403 CondARM32::Cond Cond);
404 404
405 void vmlsd(const Operand *OpDd, const Operand *OpDn, const Operand *OpDm,
406 CondARM32::Cond Cond);
407
408 void vmlss(const Operand *OpSd, const Operand *OpSn, const Operand *OpSm,
409 CondARM32::Cond Cond);
410
405 // Uses APSR_nzcv as register 411 // Uses APSR_nzcv as register
406 void vmrsAPSR_nzcv(CondARM32::Cond Cond); 412 void vmrsAPSR_nzcv(CondARM32::Cond Cond);
407 413
408 void vmuld(const Operand *OpDd, const Operand *OpDn, const Operand *OpDm, 414 void vmuld(const Operand *OpDd, const Operand *OpDn, const Operand *OpDm,
409 CondARM32::Cond Cond); 415 CondARM32::Cond Cond);
410 416
411 void vmuls(const Operand *OpSd, const Operand *OpSn, const Operand *OpSm, 417 void vmuls(const Operand *OpSd, const Operand *OpSn, const Operand *OpSm,
412 CondARM32::Cond Cond); 418 CondARM32::Cond Cond);
413 419
414 void vpop(const Variable *OpBaseReg, SizeT NumConsecRegs, 420 void vpop(const Variable *OpBaseReg, SizeT NumConsecRegs,
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610 616
611 void emitVFPsss(CondARM32::Cond Cond, IValueT Opcode, const Operand *OpSd, 617 void emitVFPsss(CondARM32::Cond Cond, IValueT Opcode, const Operand *OpSd,
612 const Operand *OpSn, const Operand *OpSm, 618 const Operand *OpSn, const Operand *OpSm,
613 const char *InstName); 619 const char *InstName);
614 }; 620 };
615 621
616 } // end of namespace ARM32 622 } // end of namespace ARM32
617 } // end of namespace Ice 623 } // end of namespace Ice
618 624
619 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H 625 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H
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