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Side by Side Diff: lib/Target/ARM/MCTargetDesc/ARMMCNaClExpander.cpp

Issue 1642253003: Auto-sandboxing: add support for a few missing ARM opcodes (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-llvm.git@master
Patch Set: Created 4 years, 10 months ago
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1 //===- ARMMCNaClExpander.cpp ------------------------------------*- C++ -*-===// 1 //===- ARMMCNaClExpander.cpp ------------------------------------*- C++ -*-===//
2 // 2 //
3 // The LLVM Compiler Infrastructure 3 // The LLVM Compiler Infrastructure
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 // 9 //
10 // This file implements the ARMMCNaClExpander class, the ARM specific 10 // This file implements the ARMMCNaClExpander class, the ARM specific
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349 349
350 void ARM::ARMMCNaClExpander::expandLoadStore(const MCInst &Inst, 350 void ARM::ARMMCNaClExpander::expandLoadStore(const MCInst &Inst,
351 MCStreamer &Out, 351 MCStreamer &Out,
352 const MCSubtargetInfo &STI) { 352 const MCSubtargetInfo &STI) {
353 switch (Inst.getOpcode()) { 353 switch (Inst.getOpcode()) {
354 case ARM::STMIA_UPD: 354 case ARM::STMIA_UPD:
355 case ARM::STMDA_UPD: 355 case ARM::STMDA_UPD:
356 case ARM::STMDB_UPD: 356 case ARM::STMDB_UPD:
357 case ARM::STMIB_UPD: 357 case ARM::STMIB_UPD:
358 358
359 case ARM::VSTMDIA:
359 case ARM::VSTMDIA_UPD: 360 case ARM::VSTMDIA_UPD:
360 case ARM::VSTMDDB_UPD: 361 case ARM::VSTMDDB_UPD:
362 case ARM::VSTMSIA:
361 case ARM::VSTMSIA_UPD: 363 case ARM::VSTMSIA_UPD:
362 case ARM::VSTMSDB_UPD: 364 case ARM::VSTMSDB_UPD:
363 365
364 case ARM::LDMIA_UPD: 366 case ARM::LDMIA_UPD:
365 case ARM::LDMDA_UPD: 367 case ARM::LDMDA_UPD:
366 case ARM::LDMDB_UPD: 368 case ARM::LDMDB_UPD:
367 case ARM::LDMIB_UPD: 369 case ARM::LDMIB_UPD:
368 370
371 case ARM::VLDMDIA:
369 case ARM::VLDMDIA_UPD: 372 case ARM::VLDMDIA_UPD:
370 case ARM::VLDMDDB_UPD: 373 case ARM::VLDMDDB_UPD:
374 case ARM::VLDMSIA:
371 case ARM::VLDMSIA_UPD: 375 case ARM::VLDMSIA_UPD:
372 case ARM::VLDMSDB_UPD: 376 case ARM::VLDMSDB_UPD:
373 377
374 case ARM::STMIA: 378 case ARM::STMIA:
375 case ARM::STMDA: 379 case ARM::STMDA:
376 case ARM::STMDB: 380 case ARM::STMDB:
377 case ARM::STMIB: 381 case ARM::STMIB:
378 382
379 case ARM::LDMIA: 383 case ARM::LDMIA:
380 case ARM::LDMDA: 384 case ARM::LDMDA:
381 case ARM::LDMDB: 385 case ARM::LDMDB:
382 case ARM::LDMIB: 386 case ARM::LDMIB:
383 return sandboxBaseDisp(Inst, *InstInfo, Inst.getOperand(0).getReg(), Out, 387 return sandboxBaseDisp(Inst, *InstInfo, Inst.getOperand(0).getReg(), Out,
384 STI); 388 STI);
389 case ARM::DMB:
390 // DMB is mayLoad but has no memory operands and needs no sandboxing
391 return Out.EmitInstruction(Inst, STI);
385 } 392 }
386 393
387 int MemIdx = getMemIdx(Inst, *InstInfo); 394 int MemIdx = getMemIdx(Inst, *InstInfo);
388 assert(MemIdx != -1); 395 assert(MemIdx != -1);
389 396
390 unsigned BaseReg = Inst.getOperand(MemIdx).getReg(); 397 unsigned BaseReg = Inst.getOperand(MemIdx).getReg();
391 bool PostIncrement = false; 398 bool PostIncrement = false;
392 399
393 switch (Inst.getOpcode()) { 400 switch (Inst.getOpcode()) {
394 case ARM::PLDi12: 401 case ARM::PLDi12:
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486 const MCSubtargetInfo &STI) { 493 const MCSubtargetInfo &STI) {
487 if (Guard) 494 if (Guard)
488 return false; 495 return false;
489 Guard = true; 496 Guard = true;
490 497
491 doExpandInst(Inst, Out, STI); 498 doExpandInst(Inst, Out, STI);
492 499
493 Guard = false; 500 Guard = false;
494 return true; 501 return true;
495 } 502 }
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