Add multi-source/dest VMOV to the integrated ARM assembler.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 2409 matching lines @@
   //
   // cccc11101D110000dddd101101M0mmmm where cccc=Cond, Ddddd=Sd, and Mmmmm=Sm.
   constexpr const char *Vmovdd = "Vmovdd";
   IValueT Dd = encodeSRegister(OpDd, "Dd", Vmovdd);
   IValueT Dm = encodeSRegister(OpDm, "Dm", Vmovdd);
   constexpr IValueT VmovddOpcode = B23 | B21 | B20 | B6;
   constexpr IValueT D0 = 0;
   emitVFPddd(Cond, VmovddOpcode, Dd, D0, Dm);
 }
 
+void AssemblerARM32::vmovdrr(const Operand *OpDm, const Operand *OpRt,
+                             const Operand *OpRt2, CondARM32::Cond Cond) {
+  // VMOV (between two ARM core registers and a doubleword extension register).
+  // ARM section A8.8.345, encoding A1:
+  //   vmov<c> <Dm>, <Rt>, <Rt2>
+  //
+  // cccc11000100xxxxyyyy101100M1mmmm where cccc=Cond, xxxx=Rt, yyyy=Rt2, and
+  // Mmmmm=Dm.
+  constexpr const char *Vmovdrr = "vmovdrr";
+  IValueT Dm = encodeDRegister(OpDm, "Dm", Vmovdrr);
+  IValueT Rt = encodeGPRegister(OpRt, "Rt", Vmovdrr);
+  IValueT Rt2 = encodeGPRegister(OpRt2, "Rt", Vmovdrr);
+  assert(Rt != RegARM32::Encoded_Reg_sp);
+  assert(Rt != RegARM32::Encoded_Reg_pc);
+  assert(Rt2 != RegARM32::Encoded_Reg_sp);
+  assert(Rt2 != RegARM32::Encoded_Reg_pc);
+  assert(Rt != Rt2);
+  assert(CondARM32::isDefined(Cond));
+  IValueT Encoding = B27 | B26 | B22 | B11 | B9 | B8 | B4 |
+                     (encodeCondition(Cond) << kConditionShift) | (Rt2 << 16) |
+                     (Rt << 12) | (getYInRegYXXXX(Dm) << 5) |
+                     getXXXXInRegYXXXX(Dm);
+  emitInst(Encoding);
+}
+
+void AssemblerARM32::vmovrrd(const Operand *OpRt, const Operand *OpRt2,
+                             const Operand *OpDm, CondARM32::Cond Cond) {
+  // VMOV (between two ARM core registers and a doubleword extension register).
+  // ARM section A8.8.345, encoding A1:
+  //   vmov<c> <Rt>, <Rt2>, <Dm>
+  //
+  // cccc11000101xxxxyyyy101100M1mmmm where cccc=Cond, xxxx=Rt, yyyy=Rt2, and
+  // Mmmmm=Dm.
+  constexpr const char *Vmovrrd = "vmovrrd";
+  IValueT Rt = encodeGPRegister(OpRt, "Rt", Vmovrrd);
+  IValueT Rt2 = encodeGPRegister(OpRt2, "Rt", Vmovrrd);
+  IValueT Dm = encodeDRegister(OpDm, "Dm", Vmovrrd);
+  assert(Rt != RegARM32::Encoded_Reg_sp);
+  assert(Rt != RegARM32::Encoded_Reg_pc);
+  assert(Rt2 != RegARM32::Encoded_Reg_sp);
+  assert(Rt2 != RegARM32::Encoded_Reg_pc);
+  assert(Rt != Rt2);
+  assert(CondARM32::isDefined(Cond));
+  IValueT Encoding = B27 | B26 | B22 | B20 | B11 | B9 | B8 | B4 |
+                     (encodeCondition(Cond) << kConditionShift) | (Rt2 << 16) |
+                     (Rt << 12) | (getYInRegYXXXX(Dm) << 5) |
+                     getXXXXInRegYXXXX(Dm);
+  emitInst(Encoding);
+}
+
 void AssemblerARM32::vmovrs(const Operand *OpRt, const Operand *OpSn,
                             CondARM32::Cond Cond) {
   // VMOV (between ARM core register and single-precision register)
   //   ARM section A8.8.343, encoding A1.
   //
   //   vmov<c> <Rt>, <Sn>
   //
   // cccc11100001nnnntttt1010N0010000 where cccc=Cond, nnnnN = Sn, and tttt=Rt.
   constexpr const char *Vmovrs = "vmovrs";
   IValueT Rt = encodeGPRegister(OpRt, "Rt", Vmovrs);
@@ skipping 249 matching lines @@
   //
   // cccc11010D101101dddd1010iiiiiiii where cccc=Cond, ddddD=BaseReg, and
   // iiiiiiii=NumConsecRegs.
   constexpr IValueT VpushOpcode =
       B27 | B26 | B24 | B21 | B19 | B18 | B16 | B11 | B9;
   emitVStackOp(Cond, VpushOpcode, OpBaseReg, NumConsecRegs);
 }
 
 } // end of namespace ARM32
 } // end of namespace Ice